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interconnect

Here are 50 public repositories matching this topic...

dpretet / axi-crossbar

Parametric AXI4 crossbar in SystemVerilog

arm asic fpga processor riscv verilog soc fpga-soc interconnect amba crossbar riscv32 axi4 axi4-lite riscv64 monodraw axi4-protocol asic-design axi4-full

Updated May 25, 2026
SystemVerilog

ucb-bar / constellation

A Chisel RTL generator for network-on-chip interconnects

hardware chisel rtl soc noc interconnect network-on-chip

Updated Nov 7, 2025
Scala

purdue-onchip / gds2Para

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

parse eda vlsi integrated-circuits interconnect gdsii spef electronic-design-automation vlsi-circuits

Updated Apr 23, 2023
C++

RoaLogic / ahb3lite_interconnect

AHB3-Lite Interconnect

switch interconnect amba ahb3-lite

Updated May 10, 2024
SystemVerilog

uuudown / Tartan

Tartan: Evaluating Modern GPU Interconnect via a Multi-GPU Benchmark Suite

gpu benchmark-suite pcie interconnect multi-gpus nvlink

Updated Sep 12, 2018
Cuda

atfox272 / AXI4-Interconnect

RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction.

axi interconnect axi4

Updated Mar 13, 2025
Verilog

Chinesezjc / dsh-interconnect

Cross-instance message/event handoff plugins for DSH (interconnect service + tools)

dsh interconnect deepseek-harness dsh-plugin

Updated Aug 25, 2026
TypeScript

KOSASIH / cosmia-core

The central repository for the Cosmia project, containing the core architecture and infrastructure for the Sidra Chain.

galaxies stars cosmos sidra interconnect intergalactic sidra-chain sidra-bank sidra-family

Updated Oct 26, 2024
JavaScript

Davxx / gem5_Garnet2.0_extensions

Fork of the gem5 simulator with Garnet2.0 and DSENT extensions

noc interconnect network-on-chip gem5-simulator dsent

Updated Jan 28, 2019
C++

neighbourhoodie / voice-of-interconnect

Offline First demo app for IBM InterConnect 2017

couchdb pwa offline-first hoodie ibm watson-services interconnect

Updated Apr 11, 2017
JavaScript

INESCTEC / interoperable-recommender-tso

The Interoperable Recommender is a data-driven solution aimed at enabling the participation of consumers in enhancing the resilience of the European energy infrastructure.

python energy paper recommender interconnect

Updated Dec 7, 2024
Python

RHsyseng / amq7

OpenShift S2I image/templates and accompanying test suite showcasing various AMQ7 broker/router topologies.

activemq openshift-templates qpid interconnect qpid-dispatch-router amq7 activemq-artemis openshift-v3

Updated Jun 1, 2021
Java

lcapossio / axiZero

Open source AXI4 / AXI4-Lite interconnect generator. Describe your bus topology in YAML, get you Verilog back

asic fpga bus verilog axi interconnect

Updated Aug 1, 2026
Verilog

PJHkorea / photonic-mesh-fng-router

A humble exploratory PoC for a hardware-native, optical timing-frozen control plane engine. Fuses inline CUDA PTX, RAII memory tunnels, and 4D JAX shard_map structures to investigate 0ns-overhead fault-tolerant routing for hyperscale distributed AI.

distributed-systems fault-tolerance zero-copy cuda high-performance-computing compiler-optimization interconnect silicon-photonics jax pytorch-extension xla custom-kernels hardware-software-co-design ahead-of-time-compilation ai-infrastructure llm-infrastructure deepseek-v4 ptx-assembly hlo-compiler

Updated Aug 9, 2026
Python

jeremyary / amq7-refarch

Test suite showcasing various AMQ 7 Reference Architecture broker/router topologies on OpenShift

activemq qpid interconnect qpid-dispatch-router amq7 activemq-artemis

Updated Oct 11, 2017
Java

Florin623 / AXI-Lite-Slave-FFT-IP

3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.

Updated Apr 13, 2024
VHDL

alinja / alpus_wb

VHDL implementation of Pipelined Wishbone B4 interconnect

fpga bus vhdl soc fpga-soc wishbone system-on-chip interconnect wishbone-bus

Updated Dec 5, 2024
VHDL

dozecat / axi_lib

SystemVerilog AXI4/AXI4-Lite RTL library

systemverilog verilator axi interconnect amba axi4

Updated Jul 30, 2026
SystemVerilog

rmarting / scale-amq-with-interconnect

Scaling AMQ 7 Brokers with AMQ Interconnect

messaging interconnect qpid-dispatch-router activemq-artemis

Updated Apr 22, 2019
Java

INESCTEC / ev-dml

Dynamic Incentives for Electric Vehicles Charging: Causal Insights on Demand Flexibility

python energy paper causality electric-vehicles interconnect incentives

Updated Nov 27, 2025
Python

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