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Xilinx / Vitis-Tutorials

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Vitis In-Depth Tutorials

embedded fpga hls embedded-systems versal xrt vitis aiengine zcu104 kria

Updated Aug 18, 2026
C

Xilinx / XRT

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Run Time for AIE and FPGA based platforms

fpga linux-kernel hip versal ryzen aie xrt npu vitis ctrlcode

Updated Sep 4, 2026
C++

Xilinx / Vitis_Accel_Examples

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Vitis_Accel_Examples

zynq xilinx soc alveo fpga-programming acap vitis

Updated Aug 31, 2026
Makefile

pavel-demin / red-pitaya-notes

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Notes on the Red Pitaya Open Source Instrument

radio linux fpga zynq dsp tcl verilog nmr xilinx sdr mca redpitaya vna vivado wspr red-pitaya vitis

Updated Aug 29, 2026
Tcl

definelicht / hlslib

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A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

cmake fpga hpc xilinx sdaccel high-level-synthesis vivado-hls intel-fpga vitis intel-fpga-opencl

Updated Jan 20, 2025
C++

fpgasystems / Vitis_with_100Gbps_TCP-IP

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100 Gbps TCP/IP stack for Vitis shells

tcp xilinx vitis network-kernel

Updated Apr 23, 2024
C++

Xilinx / xup_vitis_network_example

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VNx: Vitis Network Examples

networking xilinx alveo vnx vitis vitis-network alveo-card

Updated Aug 25, 2025
Jupyter Notebook

jiwoonl / Event-Driven-Spiking-Neural-Network-Accelerator-for-FPGA

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Energy-efficient Event-driven Spiking Neural Network accelerator for FPGA with PyTorch integration

pytorch embedded-systems computational-neuroscience verilog xilinx spiking-neural-networks vivado pynq verilog-hdl snn neuromorphic-computing leaky-integrate-and-fire-neuron lif-neuron spiking-neural-network vitis hardware-accelerator lif-model

Updated Aug 28, 2026
VHDL

Xilinx / Vitis_Model_Composer

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Vitis Model Composer Examples and Tutorials

fpga hls acap vitis aiengine

Updated Jun 25, 2026
C++

Xilinx / xup_compute_acceleration

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Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware

fpga xilinx vitis xup

Updated Jul 24, 2024
C++

FedericoSerafini / HLS-CNN

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High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.

asic fpga stream hls pipeline hardware accelerator parallel cnn rtl synthesis hdl high-level-synthesis vitis

Updated Jul 25, 2024
C

spcl / apfp

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FPGA acceleration of arbitrary precision floating point computations.

fpga hls hpc bignum arbitrary-precision high-performance-computing xilinx gmp mpfr high-level-synthesis vivado-hls vitis multiple-precision

Updated May 17, 2022
C++

lvgl / lv_port_xilinx_zedboard_vitis

Sponsor

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This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals

embedded usb tcp amd mouse freertos ntp xilinx vivado touchscreen zedboard vga digilent lvgl vitis

Updated Oct 12, 2023
C

noecochetel / North_American_Vitis_Pangenome

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Construct and Analyze the North American Vitis pangenome

genomics grapevine pangenomics vitis

Updated Aug 19, 2025
R

dsa-shua / FPGA-SystolicArray

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Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis

sdk fpga hardware accelerator matrix project matrix-multiplication verilog xilinx vivado systemverilog hardware-designs hdl hardware-acceleration zynq-7000 systolic-arrays pynq-z2 vitis

Updated Feb 16, 2024
SystemVerilog

IMPETUS-UdeS / rule4ml

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Resource Utilization and Latency Estimation for ML on FPGA.

python machine-learning fpga neural-network hls keras prediction pytorch vivado regression-models resource-utilization onnx surrogate-models vitis

Updated Apr 11, 2026
Python

jasonlin316 / GCN-Inference-Acceleration-HLS

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An end-to-end GCN inference accelerator written in HLS

neural-network hls end-to-end inference xilinx gcn vitis

Updated Apr 5, 2022
C++

pavel-demin / eclypse-z7-notes

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Notes on the Eclypse Z7 development board

fpga zynq dsp tcl verilog xilinx sdr vivado digilent vitis eclypse-z7

Updated Apr 9, 2026
C

salehjg / DeepPoint-V2-FPGA

Sponsor

Star

The code repository of DGCNN on FPGA: Acceleration of The Point Cloud Classifier Using FPGAs

fpga deep-learning hls xilinx pointcloud sdaccel shapenet-dataset modelnet-dataset vitis

Updated Mar 6, 2023
C++

ribesstefano / Mapping-Multiple-LSTM-Models-on-FPGAs

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Includes the SVD-based approximation algorithms for compressing deep learning models and the FPGA accelerators exploiting such approximation mechanism, as described in the paper Mapping multiple LSTM models on FPGAs.

machine-learning fpga hls cpp14 xilinx fpga-accelerator svd-matrix-factorisation vitis

Updated Mar 3, 2023
Jupyter Notebook

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vitis

Here are 167 public repositories matching this topic...

Xilinx / Vitis-Tutorials

Xilinx / XRT

Xilinx / Vitis_Accel_Examples

pavel-demin / red-pitaya-notes

definelicht / hlslib

fpgasystems / Vitis_with_100Gbps_TCP-IP

Xilinx / xup_vitis_network_example

jiwoonl / Event-Driven-Spiking-Neural-Network-Accelerator-for-FPGA

Xilinx / Vitis_Model_Composer

Xilinx / xup_compute_acceleration

FedericoSerafini / HLS-CNN

spcl / apfp

lvgl / lv_port_xilinx_zedboard_vitis

noecochetel / North_American_Vitis_Pangenome

dsa-shua / FPGA-SystolicArray

IMPETUS-UdeS / rule4ml

jasonlin316 / GCN-Inference-Acceleration-HLS

pavel-demin / eclypse-z7-notes

salehjg / DeepPoint-V2-FPGA

ribesstefano / Mapping-Multiple-LSTM-Models-on-FPGAs

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