pulp-platform · FrancescoConti · Aug 5, 2026 · Aug 5, 2026 · Aug 5, 2026 · Aug 5, 2026
diff --git a/.github/verible.waiver b/.github/verible.waiver
@@ -0,0 +1,10 @@
+# Copyright 2025 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Disable line length check
+waive --rule=line-length
+# Disable parameter style check
+waive --rule=parameter-name-style
+# Disable default check in case statements
+waive --rule=case-missing-default
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -0,0 +1,96 @@
+# Copyright 2025 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Run functional regression checks
+name: ci
+on: [push, pull_request]
+
+jobs:
+  hwpe-tests:
+    name: hwpe-tests (NB_CONTEXT=${{ matrix.nb_context }})
+    runs-on: ubuntu-latest
+    strategy:
+      fail-fast: false
+      # NB_CONTEXT is a Verilator elaboration-time parameter (-GNB_CONTEXT,
+      # see target/sim/verilator/verilator.mk), so each value needs its own
+      # model build: run the whole regression once per context count (same
+      # reasoning as RedMulE's ProbStall matrix in its own ci.yml).
+      matrix:
+        nb_context: [2, 4]
+    env:
+      N_PROC: 4
+      Target: verilator
+      Verilator: verilator
+      VERILATOR_VERSION: "5.046"
+      CCACHE_BASEDIR: ${{ github.workspace }}
+      CCACHE_COMPILERCHECK: content
+
+    steps:
+    - uses: actions/checkout@v4
+
+    - name: Set up ccache
+      uses: hendrikmuhs/ccache-action@v1
+      with:
+        key: ${{ runner.os }}-verilator-${{ env.VERILATOR_VERSION }}-nbcontext${{ matrix.nb_context }}
+        max-size: 2G
+
+    - name: Install Verilator (prebuilt)
+      uses: veryl-lang/setup-verilator@v1
+      with:
+        version: ${{ env.VERILATOR_VERSION }}
+
+    - name: Install uv
+      uses: astral-sh/setup-uv@v8.3.2
+
+    - name: Install PeakRDL & prettytable
+      run: |
+        uv tool install peakrdl-cli --with peakrdl-regblock --with peakrdl-html --with peakrdl-cheader
+        uv venv --python python3 venv
+        source venv/bin/activate
+        uv pip install prettytable pyyaml junit-xml
+
+    - name: Install bender
+      run: |
+        make bender
+
+    - name: Add installed tools to PATH
+      run: |
+        echo "$(pwd)/vendor/install/cargo/bin" >> $GITHUB_PATH
+        echo "$HOME/.local/bin" >> $GITHUB_PATH
+        echo "$(pwd)/venv/bin" >> $GITHUB_PATH
+
+    - name: Build verilator model
+      run: |
+        make hw-build-all target=verilator NbContext=${{ matrix.nb_context }} VerilatorJobs=4
+
+    - name: Run Tests
+      run: |
+        scripts/ci-regression.sh
+
+    # Not present in RedMulE's ci.yml: surface the per-test transcripts as a
+    # downloadable artifact whenever the regression fails, since the "[TB] -
+    # Fail!" / $error output that pinpoints the failure only lives in
+    # target/sim/verilator/transcript_* on the runner and is otherwise lost
+    # once the job ends.
+    - name: Upload transcripts on failure
+      if: failure()
+      uses: actions/upload-artifact@v4
+      with:
+        name: transcripts-nbcontext${{ matrix.nb_context }}
+        path: target/sim/verilator/transcript_*
+
+  # Aggregate gate with a fixed name: the matrix above reports one check per
+  # NB_CONTEXT value, so branch rulesets cannot pin a stable context to it.
+  # This is the job the ruleset requires -- keep its name in sync with the
+  # required status check.
+  run-hwpe-tests:
+    name: run-hwpe-tests
+    runs-on: ubuntu-latest
+    needs: hwpe-tests
+    if: always()
+    steps:
+    - name: Check matrix result
+      run: |
+        echo "hwpe-tests result: ${{ needs.hwpe-tests.result }}"
+        [ "${{ needs.hwpe-tests.result }}" = "success" ]
diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml
@@ -0,0 +1,78 @@
+# Copyright 2025 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+name: lint
+
+on: [ push, pull_request, workflow_dispatch ]
+
+jobs:
+
+  lint-license:
+    runs-on: ubuntu-latest
+    steps:
+    -
+      name: Checkout
+      uses: actions/checkout@v3
+    -
+      name: Check license
+      uses: pulp-platform/pulp-actions/lint-license@v2
+      with:
+        license: |
+          Copyright (\d{4}(-\d{4})?\s)?.*
+          (Solderpad Hardware License, Version 0.51|Licensed under the Apache License, Version 2.0), see LICENSE for details.
+          SPDX-License-Identifier: (SHL-0.51|Apache-2.0)
+        # Exclude generated/vendored content that falls outside this
+        # three-line header convention:
+        #  - rtl/rdl-example is peakrdl-generated (make regif) and gitignored,
+        #    so it is normally absent from a fresh checkout anyway;
+        #  - uloop-example/ ships its own Apache-2.0 LICENSE.sw.txt with a
+        #    differently worded, pre-existing header ("See LICENSE.sw.txt
+        #    for details", no SPDX-License-Identifier line) and is not part
+        #    of this WP's file set to rewrite.
+        # Waived non-RTL build/manifest files, which carry no header today:
+        #  - Bender.yml and src_files.yml are dependency manifests;
+        #  - rtl/rdl.sh and sim/* are the legacy QuestaSim helper scripts
+        #    (the current Verilator flow lives under target/sim, which is
+        #    NOT waived and is checked normally).
+        # Patterns are fnmatch'd against the repo-relative path, so `sim/*`
+        # matches only the top-level sim/ tree, not target/sim/.
+        exclude_paths: |
+          *.md
+          LICENSE*
+          uloop-example/*
+          rtl/rdl-example/*
+          *.rdl
+          Bender.yml
+          src_files.yml
+          rtl/rdl.sh
+          sim/*
+
+  lint-sv:
+    runs-on: ubuntu-latest
+    steps:
+    -
+      name: Checkout
+      uses: actions/checkout@v3
+    -
+      name: Run Verible
+      uses: chipsalliance/verible-linter-action@main
+      with:
+        paths: rtl target/sim/src
+        # rtl/rdl-example is peakrdl-generated output (gitignored, produced
+        # by `make regif`); it will not pass style lint and is excluded the
+        # same way RedMulE excludes individual files here, via a path
+        # prefix matched against the discovered file list.
+        exclude_paths: |
+          rtl/rdl-example
+        extra_args: "--waiver_files .github/verible.waiver"
+        github_token: ${{ secrets.GITHUB_TOKEN }}
+        fail_on_error: true
+        reviewdog_reporter: github-check
+        log_file: verible-verilog-lint.log
+    -
+      name: Upload Verible Artifacts
+      uses: actions/upload-artifact@v4
+      with:
+        name: lint-sv-artifacts
+        path: verible-verilog-lint.log
diff --git a/.gitignore b/.gitignore
@@ -0,0 +1,15 @@
+# Bender / vendored tooling
+.bender/
+vendor/
+
+# Generated register interface (rtl/rdl.sh output)
+rtl/rdl-example/
+
+# Verilator simulation artifacts
+target/sim/verilator/obj_dir*/
+target/sim/verilator/compile.verilator.tcl
+target/sim/verilator/transcript_*
+target/sim/verilator/*.vcd
+
+# Python
+__pycache__/
diff --git a/Bender.lock b/Bender.lock
@@ -0,0 +1,22 @@
+packages:
+  common_cells:
+    revision: 1281545696eb3fcba50ec5b4275993476a3c710e
+    version: 1.40.0
+    source:
+      Git: https://github.com/pulp-platform/common_cells.git
+    dependencies:
+    - common_verification
+    - tech_cells_generic
+  common_verification:
+    revision: fb1885f48ea46164a10568aeff51884389f67ae3
+    version: 0.2.5
+    source:
+      Git: https://github.com/pulp-platform/common_verification.git
+    dependencies: []
+  tech_cells_generic:
+    revision: 3a3de73632a06826b1bd9c65a0a2e92b32016845
+    version: 0.2.14
+    source:
+      Git: https://github.com/pulp-platform/tech_cells_generic.git
+    dependencies:
+    - common_verification
diff --git a/Bender.yml b/Bender.yml
@@ -33,3 +33,19 @@ sources:
       - rtl/deprecated/hwpe_ctrl_regfile.sv
       # Level 4
       - rtl/deprecated/hwpe_ctrl_slave.sv
+
+  - target: hwpe_ctrl_test
+    include_dirs:
+      - rtl/rdl-example
+    files:
+      - rtl/rdl-example/hwpe_ctrl_regif_example_pkg.sv
+      - rtl/rdl-example/hwpe_ctrl_regif_example.sv
+      - target/sim/src/hwpe_ctrl_target_wrap.sv
+      - target/sim/src/hwpe_ctrl_target_tb.sv
+      - target/sim/src/hwpe_ctrl_target_tb_wrap.sv
+      - target/sim/src/hwpe_ctrl_partial_mult_tb.sv
+      - target/sim/src/hwpe_ctrl_partial_mult_tb_wrap.sv
+      - target/sim/src/hwpe_ctrl_seq_mult_tb.sv
+      - target/sim/src/hwpe_ctrl_seq_mult_tb_wrap.sv
+      - target/sim/src/hwpe_ctrl_uloop_tb.sv
+      - target/sim/src/hwpe_ctrl_uloop_tb_wrap.sv
diff --git a/Makefile b/Makefile
@@ -0,0 +1,53 @@
+# Copyright 2026 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Top-level Makefile
+
+# Paths to folders
+RootDir    := $(dir $(abspath $(firstword $(MAKEFILE_LIST))))
+TargetDir  := $(RootDir)target
+SimDir     := $(TargetDir)/sim
+
+Bender ?= bender
+
+target ?= verilator
+TargetPath := $(SimDir)/$(target)
+
+# Included makefrags
+include $(TargetPath)/$(target).mk
+include bender_common.mk
+include bender_sim.mk
+
+# Useful Parameters
+gui ?= 0
+
+SHELL := /bin/bash
+
+# Regenerate the example register interface (rtl/rdl-example) from the
+# PeakRDL source (rtl/hwpe_ctrl_regif_example.rdl).
+.PHONY: regif regif-clean
+regif:
+	cd rtl && ./rdl.sh
+
+regif-clean:
+	rm -rf rtl/rdl-example
+
+clean-all:
+	rm -rf $(RootDir).bender
+
+# Install tools
+VendorDir  ?= $(RootDir)vendor
+InstallDir ?= $(VendorDir)/install
+# Bender (installed from prebuilt release binaries, no Rust toolchain needed)
+BenderVersion ?= 0.32.1
+CargoInstallDir := $(InstallDir)/cargo
+
+bender: $(CargoInstallDir)/bin/bender
+
+$(CargoInstallDir)/bin/bender:
+	mkdir -p $(InstallDir)
+	curl --proto '=https' --tlsv1.2 -sSfL https://github.com/pulp-platform/bender/releases/download/v$(BenderVersion)/bender-installer.sh > $(InstallDir)/bender-installer.sh
+	BENDER_INSTALL_DIR=$(CargoInstallDir) BENDER_NO_MODIFY_PATH=1 BENDER_DISABLE_UPDATE=1 \
+		sh $(InstallDir)/bender-installer.sh
+	rm -f $(InstallDir)/bender-installer.sh
diff --git a/bender_common.mk b/bender_common.mk
@@ -0,0 +1,13 @@
+# Copyright 2025 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Makefragment holding common bender flags shared across simulation and
+# (future) synthesis flows. hwpe-ctrl has no core-specific configuration
+# (unlike e.g. RedMulE, which uses this file to select cv32e40p/cv32e40x
+# flags), so common_targs/common_defs are intentionally left empty here.
+# The file is kept as a parity placeholder so downstream flows can simply
+# append to common_targs/common_defs without needing to guard the include.
+
+common_targs +=
+common_defs  +=
diff --git a/bender_sim.mk b/bender_sim.mk
@@ -0,0 +1,8 @@
+# Copyright 2025 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Makefragment for simulation-only bender flags.
+
+sim_targs += -t rtl
+sim_targs += -t hwpe_ctrl_test
diff --git a/rtl/deprecated/hwpe_ctrl_regfile.sv b/rtl/deprecated/hwpe_ctrl_regfile.sv
@@ -1,3 +1,7 @@
+// Copyright 2014-2018 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
 /*
  * hwpe_ctrl_regfile.sv
  * Francesco Conti <f.conti@unibo.it>

diff --git a/rtl/deprecated/hwpe_ctrl_regfile_ff.sv b/rtl/deprecated/hwpe_ctrl_regfile_ff.sv
@@ -1,3 +1,7 @@
+// Copyright 2014-2018 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
 /* 
  * hwpe_ctrl_regfile_latch.sv
  * Francesco Conti <fconti@iis.ee.ethz.ch>

diff --git a/rtl/deprecated/hwpe_ctrl_regfile_latch.sv b/rtl/deprecated/hwpe_ctrl_regfile_latch.sv
@@ -1,3 +1,7 @@
+// Copyright 2014-2018 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
 /* 
  * hwpe_ctrl_regfile_latch.sv
  * Francesco Conti <fconti@iis.ee.ethz.ch>

diff --git a/rtl/deprecated/hwpe_ctrl_regfile_latch_test_wrap.sv b/rtl/deprecated/hwpe_ctrl_regfile_latch_test_wrap.sv
@@ -1,3 +1,7 @@
+// Copyright 2014-2018 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
 /* 
  * hwpe_ctrl_regfile_latch.sv
  * Francesco Conti <fconti@iis.ee.ethz.ch>

diff --git a/rtl/deprecated/hwpe_ctrl_slave.sv b/rtl/deprecated/hwpe_ctrl_slave.sv
@@ -1,3 +1,7 @@
+// Copyright 2014-2018 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
 /*
  * hwpe_ctrl_slave.sv
  * Francesco Conti <f.conti@unibo.it>

diff --git a/rtl/hwpe_ctrl_interfaces.sv b/rtl/hwpe_ctrl_interfaces.sv
@@ -1,3 +1,7 @@
+// Copyright 2014-2018 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
 /*
  * hwpe_ctrl_interfaces.sv
  * Francesco Conti <f.conti@unibo.it>

diff --git a/rtl/hwpe_ctrl_package.sv b/rtl/hwpe_ctrl_package.sv
@@ -1,3 +1,7 @@
+// Copyright 2014-2018 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
 /*
  * hwpe_ctrl_package.sv
  * Francesco Conti <f.conti@unibo.it>

diff --git a/rtl/hwpe_ctrl_partial_mult.sv b/rtl/hwpe_ctrl_partial_mult.sv
@@ -1,3 +1,7 @@
+// Copyright 2014-2026 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
 /* 
  * hwpe_ctrl_partial_mult.sv
  * Francesco Conti <f.conti@unibo.it>