Actions: UCSBarchlab/PyRTL
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FastSimulation's handling of slice (s) LogicNets for ~15% speedup.
Run Python tests
#250:
Pull request #494
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fdxmw
FastSimulation's handling of slice (s) LogicNets for ~15% speedup.
Run Python tests
#249:
Pull request #494
opened
by
fdxmw
simple_func di…
Run Python tests
#248:
Commit d3eee38
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fdxmw
simple_func di…
Build and publish release
#108:
Commit d3eee38
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fdxmw
simple_func dict out of _execute
Run Python tests
#247:
Pull request #493
opened
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fdxmw
name_scope is a context manager that prepends prefixes to WireVector and MemBlock names
Run Python tests
#246:
Pull request #492
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fdxmw
rtllib documentation cleanup (#491)
Build and publish release
#106:
Commit 0139256
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fdxmw
rtllib documentation cleanup (#491)
Run Python tests
#242:
Commit 0139256
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fdxmw
rtllib documentation cleanup
Run Python tests
#241:
Pull request #491
synchronize
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fdxmw
rtllib documentation cleanup
Run Python tests
#240:
Pull request #491
synchronize
by
fdxmw
rtllib documentation cleanup
Run Python tests
#239:
Pull request #491
synchronize
by
fdxmw
rtllib documentation cleanup
Run Python tests
#238:
Pull request #491
synchronize
by
fdxmw
rtllib documentation cleanup
Run Python tests
#237:
Pull request #491
opened
by
fdxmw