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tighten design clocks #4456

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tighten design clocks #4456

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8ffcce3
use latest openroad
eder-matheus Aug 21, 2026
94e2b1c
tighten clock period of multiple designs
eder-matheus Aug 21, 2026
6ada18b
Merge branch 'master' of https://github.com/The-OpenROAD-Project-priv…
eder-matheus Aug 21, 2026
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2 changes: 1 addition & 1 deletion flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ current_design jpeg_encoder

set clk_name clk
set clk_port_name clk
set clk_period 680
set clk_period 545
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# Match the old set_input/output_delay = 0.2 * clk_period budget, as
# optimization targets only (no set_input/output_delay — see rationale in
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38 changes: 19 additions & 19 deletions flow/designs/asap7/jpeg/rules-base.json
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Original file line number Diff line number Diff line change
Expand Up @@ -10,71 +10,71 @@
"level": "warning"
},
"synth__design__instance__area__stdcell": {
"value": 7008.24,
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Expand All @@ -90,23 +90,23 @@
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}
5,816 changes: 2,908 additions & 2,908 deletions flow/designs/nangate45/bp_multi_top/constraint.sdc
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44 changes: 22 additions & 22 deletions flow/designs/nangate45/bp_multi_top/rules-base.json
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Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
{
"synth__canonical_netlist__hash": {
"value": "98c720a402bfb0506bdaf4c77b53c8ba57e7740e",
"value": "05dd376ac4f924e7272c418de710361e65e336c7",
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"level": "warning"
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"value": "c97c7f2b4cdb8bf8a9c05268ca52302047fcb33c",
"compare": "==",
"level": "warning"
},
Expand All @@ -18,63 +18,63 @@
"compare": "=="
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"placeopt__design__instance__area": {
"value": 574454,
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"placeopt__design__instance__count__stdcell": {
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Expand All @@ -86,27 +86,27 @@
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}
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