Open, reproducible, local-first silicon tooling — the EDA toolchain, sign-off engines, and open PDKs behind Vyges™.

vyges-tools is the home for the tooling that turns RTL into silicon: the Vyges command-line interface, the Loom open EDA sign-off suite, reproducible from-source builds of the open-source EDA tools, and a tool-agnostic catalog of open process design kits. Everything here runs on your machine — no cloud lock-in, no per-seat licenses — and is pinned so a build today reproduces the same result tomorrow.

One binary for the whole flow: install and manage IP, PDKs, and the Loom sign-off engines, then drive them from the command line or an MCP-aware assistant.

• cli — prebuilt binaries + one-line installers (macOS · Linux · Windows), a Homebrew tap, and the catalog / PDK / Loom-engine installers.
• Docs: https://docs.vyges.com

Loom is a suite of fast, deterministic, local engines that share one design-data spine: the engines that build the block, the optimizers that close the loop, and the checks that prove it. One declarative job file in, one standard artifact out, and the next engine reads it directly — no glue scripts, no silent copy-drift. Run each as vyges loom <engine>.

• opendb — safe Rust API over OpenROAD's OpenDB: ECO surgery, DEF I/O, a typed query surface, and 2.5D/3D chiplet assembly (read a 3Dblox stack, check its structure, verify the die-to-die interfaces connect, draw it)
• opendb-lib — standalone from-source build + FFI for libodb, pinned to an exact OpenROAD commit
• loom — shared readers (Verilog · Liberty · SDC · SPEF) + the in-memory design database
• layout — clean-room geometry kernel: GDSII and OASIS read/write, polygon booleans, flatten. A foundation library, not a sign-off engine — it emits geometry, not a verdict
• geom — shared layout primitives + uniform-grid spatial index
• events — canonical structured events + tracing bridge, so every engine reports the same way

The floorplan and its rows, the well taps and endcaps, the power grid, the IO pins and pad ring, and the fill that meets density. They write straight into the same design database the rest of the suite reads — no DEF round-trip, no exchange format in between — so the block you sign off is the block you built. Placement, CTS and routing stay the flow's job.

• ifp — floorplan & rows: die/core area, the site grid, and the rows every later stage places into (hybrid sites and row parity included)
• tap — well taps & endcaps: cuts rows around macros and places the physical cells that keep wells tied and row ends legal
• pdn — power grid: rings, straps, follow pins and the vias that stitch the layers, then publishes the supply nets as block terminals
• ppl — IO pin placement: optimal matching per section, honouring excluded regions, region constraints, pin groups and mirrored pairs
• pad — IO ring & pads: the ring of IO rows around the die, with legality checked layer by layer rather than by bounding box
• fin — density fill: metal fill until every layer meets its density floor; clears existing fill first, so re-running is idempotent

• Timing & SI — sta-si: WNS/TNS sign-off with crosstalk + statistical OCV
• Power, IR & thermal — power · em-ir · thermal
• Parasitics — extract: routed layout → SPEF
• Characterization — char: SPICE + PDK models → Liberty (NLDM + CCS)
• Layout correctness — lvs: name-independent graph match, with the divergence named
• Analog measurement — meas: SNR/SINAD/THD/SFDR from a tone; gain, bandwidth, phase margin from a sweep
• Process damage — ant: antenna ratios on the routed database, naming the gate and the layer

Netlist in, better netlist out, every move scored by the same sta-si timer.

• resize — gate sizing · vt-swap — leakage/speed trade (iso-footprint)
• buffer-insert — transition fixup · hold-fix — post-route hold
• remap — logic-level area recovery via multi-output covering, equivalence-checked

• drc — width, spacing, area, density, antenna, enclosure on GDS/OASIS (+ metal fill generation)

• cdc — unsynchronized clock-domain crossings, named

• glitch — reconvergent-fanout hazards a cycle-based simulator steps over

• lec — proves two netlists compute the same function, or hands you the input where they differ

• gds-view — headless GDS/OASIS → layered SVG, overlaying exactly where DRC or LVS flagged a problem

• See it run → the AI-driven sign-off dashboard: a stock, general-purpose LLM drives the real Loom engines through vyges mcp, picking each tool and forming its arguments from the engine descriptors alone.

• Product page: https://vyges.com/products/loom

Headless, multi-arch (amd64 + arm64) builds of the open-source EDA tools — pinned to exact upstream commits, built from source on CI, published to GHCR.

• vyges-yosys — Yosys + ABC + OpenSTA (synthesis + timing)
• vyges-openroad — OpenROAD (RTL → GDS)
• vyges-klayout — headless, Qt-free KLayout + GDS renderer
• vyges-ngspice — OSDI / OpenVAF-enabled ngspice
• vyges-sim — Verilator + cocotb simulation substrate
• vyges-mockturtle — reproducible builds of the multi-output technology mapper behind remap
• vybox-eda — one light container composing them all, for digital + analog + mixed-signal flows
• vyges-iic-osic-tools — IIC-OSIC-TOOLS composed with the Vyges CLI + Loom engines, for analog and mixed-signal work

A tool-agnostic catalog of open process design kits, presented uniformly so any flow can consume them.

• pdk-catalog — the index + full PDK descriptors
• pdk-releases — Vyges-built, ciel-compatible open-PDK releases
• Mirrors: open_pdks (sky130 · gf180mcu) · ihp-open-pdk (SG13G2) · ihp-sg13cmos5l · asap7 · nangate45 · icsprout55

vyges-tools is operated by TrustStix Inc (California, USA — C Corporation). The tools here are free and open; operational costs (build infrastructure, hosting, curation) are absorbed by TrustStix. We treat this toolchain as public infrastructure for the open-silicon ecosystem.

• Main site: https://vyges.com
• Products: https://vyges.com/products
• Loom: https://vyges.com/products/loom
• Loom testbench (live): https://vyges.github.io/vyges-loom-testbench/
• VyCatalog: https://vyges.com/products/vycatalog
• Docs: https://docs.vyges.com
• Contact: https://vyges.com/contact
• Sponsor: https://github.com/sponsors/vyges-ip