spectre-simulation

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SURIYA-R-K / 4bit-Ripple-Carry-Adder-CMOS-Cadence-Virtuoso

Transistor-level design and transient simulation of a 4-bit Ripple Carry Adder using CMOS logic in Cadence Virtuoso (90 nm GPDK).

vlsi cadence-virtuoso cadence cmos analog-design ripple-carry-adder digital-vlsi transistor-level 90nm-technology spectre-simulation

Updated Jan 10, 2026

semioc / semioc.github.io

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Истории автомобилей

milbet languages-version w610 paddleocr-vl spectre-simulation monesy-cs2

Updated Jun 26, 2026
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swapnil54 / JITTER-based-TRNG-on-Cadence

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Custom VLSI design of a Jitter-Based True Random Number Generator (TRNG) with dynamic selection bit reconfigurability in Cadence Virtuoso. Features dual-VCOs, NLFSR, and 6T SRAM cells.

sram vlsi cadence-virtuoso hardware-security analog-ic-design trng entropy-source vco spectre-simulation phase-jitter

Updated May 27, 2026
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