logicsynthesis

Here are 3 public repositories matching this topic...

LAKSHMAN1410 / PUF-for-Secure-Hardware-Authentication-FPGA-ASIC-Implementation-

Design and implementation of a hybrid XOR-based Arbiter Physical Unclonable Function (PUF) on FPGA, followed by ASIC synthesis , enabling lightweight and secure hardware authentication with enhanced uniqueness, entropy, and reliability.

asic fpga rtl verilog xilinx uart vlsi basys3 puf gatelevel securehardware logicsynthesis

Updated Feb 17, 2026
Tcl

ee23b020 / Image-Enhancement-using-Verilog

Star

Implemented image processing in Verilog by converting BMP (Bitmap) image data into hex format and using FSMs (Finite State Machines) to perform brightness adjustment and color inversion. Verified synthesizability of the design using Yosys synthesis tool to ensure hardware compatibility.

verilog logicsynthesis

Updated Jun 22, 2025
Verilog

mortimerscattershot606 / PUF-for-Secure-Hardware-Authentication-FPGA-ASIC-Implementation-

Star

asic fpga rtl verilog xilinx uart vlsi basys3 puf gatelevel securehardware logicsynthesis

Updated Sep 1, 2026
Tcl

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