FPGA interface to work with cdce62005 clock synthesizer
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Updated
May 31, 2018 - VHDL
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fpga-interface
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A tactical software bridge and hardware translation layer connecting 1970s UNIVAC mainframes (CP-642B / AN/UYK-7) to modern Aegis Combat System DDS networks via MIL-STD-1397 to Ethernet conversion.
cpp17 opendds fpga-interface real-time-networking univac legacy-modernization defense-tech cms-2 aegis-combat-system dds-middleware mil-std-1397 tactical-software
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Updated
Jun 30, 2026 - Python
A tactical software bridge and hardware translation layer connecting 1970s UNIVAC mainframes (CP-642B / AN/UYK-7) to modern Aegis Combat System DDS networks via MIL-STD-1397 to Ethernet conversion.
cpp17 opendds fpga-interface real-time-networking univac legacy-modernization defense-tech cms-2 aegis-combat-system dds-middleware mil-std-1397 tactical-software
-
Updated
Jun 19, 2026 - Python
A tactical software bridge and hardware translation layer connecting 1970s UNIVAC mainframes (CP-642B / AN/UYK-7) to modern Aegis Combat System DDS networks via MIL-STD-1397 to Ethernet conversion.
cpp17 opendds fpga-interface real-time-networking univac legacy-modernization defense-tech cms-2 aegis-combat-system dds-middleware mil-std-1397 tactical-software
-
Updated
Jun 30, 2026 - Python
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