bram

verilog example to drive PCM5102 DAC with FPGA

Hardware and Software Co-design implementations

Multi-port BRAM IP for ASIC and FPGA

Galaga Arcade Core

Digital Systems Course Project: Fake Currency Detection in Verilog using Basys3 FPGA and MATLAB

PC Engine/TurboGrafx BRAM Save Data Manager

Experimental study and analysis on the effect of aggressive voltage underscaling on the reliability of COTS FPGAs: https://ieeexplore.ieee.org/abstract/document/8574581/

FPGA Implementation of Full Search Block matching using an asynchronous handshake based FSM.

Processor supporting ARM architecture made in VHDL as a part of COL216 - Computer Architecture

A BRAM-based digital function generator implemented in Verilog on the ZedBoard. Generates sine, square, triangular, and sawtooth waveforms using BRAM lookup tables.

Order book v3 - Advanced features and optimizations

Flappy Bird core for MiSTer, MiST, DeMiSTify, Xilinx, GoWin, ...

Arcade Pooyan core

This project implements a PicoRV32 processor with an integrated HDMI text output.

VGA IP Core using a dual-port BRAM as a frame buffer (shared BRAM access)

Hardware order book with 8 parallel BRAM-based books - Sub-microsecond order processing (120-170ns), 256 price levels, BBO tracking. FPGA trading core.

Demistification of Tatung Einstein micro computer

Demistify example and tutorial on how to demistify

Enhanced FPGA order book v2 - Improved resource utilization and timing optimization

A Verilog implementation of a deeply pipelined AES-128 encryption core for FPGAs. Evaluates trade-offs between speed and area utilization through LUT-based (speed-optimized) and BRAM T-Table (resource-optimized) pipeline architectures.