🔧 B.Tech ECE Student | Aspiring Design Verification / RTL Engineer | VLSI Enthusiast

Welcome to my GitHub profile! I’m focused on RTL design and digital verification using Verilog and SystemVerilog, with hands-on experience building and verifying communication protocols and digital IPs. This repository showcases my projects, verification environments, assertions, and continuous learning in VLSI.

• 🎓 B.Tech Electronics & Communication Engineering student
• 💻 Hands-on experience with Verilog and SystemVerilog
• 🔍 Focused on RTL Design and Design Verification
• 🧪 Experienced in developing transaction-based, self-checking verification environments
• 🎲 Hands-on with constrained-random stimulus and scoreboard-based verification
• 📐 Experience with SystemVerilog Assertions (SVA) for protocol and RTL verification
• 🔗 Worked with protocols and architectures including AXI4-Lite, APB, SPI, I2C, UART, and FIFO
• 📊 Interested in Digital IC Design, SoC Verification, RTL Development, and VLSI
• 🚀 Currently strengthening my knowledge of SystemVerilog and UVM

• Verilog HDL
• SystemVerilog
• Transaction-Based Verification
• Constrained-Random Verification
• Self-Checking Testbenches
• Scoreboarding
• Reference Models
• Mailbox-Based Communication
• Virtual Interfaces
• SystemVerilog Assertions (SVA)

• RTL Design
• FSM-Based Design
• FIFO Architectures
• Digital Logic Design
• Protocol-Based IP Design
• Synthesizable RTL

• AXI4-Lite
• APB
• SPI
• I2C
• UART

• EDA Playground
• GTKWave
• Riviera-PRO

Here are some of the projects I’ve worked on:

• 🔸Verilog Basics → Adders, Multiplexers, Encoders, Flip-Flops, Counters, Registers, FIFO
• 🔸UART Protocol → TX/RX design with baud rate generator and testbench
• 🔸SPI Protocol → SPI Master–Slave design & verification
• 🔸I2C Protocol → I2C Master Slave (Read/Write operations with testbench)
• 🔸Axi-Lite protocol → Register-based communication with 5-channel handshake
• 🔸Fifo Architecture → Synchronous FIFO (Single Clock with flags and testbench)
• 🔸APB Protocol → APB Slave Design and Verification

• 🔬 Deepening SystemVerilog-based Design Verification
• 📚 Learning and implementing UVM concepts
• 📊 Building stronger understanding of functional verification and coverage
• 🧪 Improving constrained-random and assertion-based verification
• 🔗 Strengthening knowledge of AMBA and serial communication protocols
• 💼 Preparing for Design Verification / RTL Engineering internships and entry-level opportunities

I’m particularly interested in opportunities involving:

• Design Verification
• RTL Design
• SoC Verification
• Digital IC Design
• VLSI / Semiconductor Engineering

I enjoy understanding how digital systems work at the RTL level and building verification environments that can systematically detect design and protocol issues.

When I’m not coding RTL or debugging testbenches, I write poetry and explore creative expression ✍️

• 💼 LinkedIn
• 📧 Email

⭐ Thanks for visiting my profile! Feel free to explore my repositories and verification projects.