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This repo contains a ARM based CPU written in VHDL.
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It is divided into 2 modules: datapath and controller, with each having their own submodules/entities.
- Is a integrated design consisting of functional units:
- ALU
- Multipliers
- Shifter
- Register File, registers
- Muxes and extenders.
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Controller determines the operation of the datapath, by passing control signals to various multiplexers. It controls the data flow through the datapath.
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It consists of the following sub-modules:
- Instruction Decode
- Main Controller
- ALU Controller
- Branch Controller
- Controller FSM:
- Schematic:
