chore: Split serializer from PHY - #34
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Extract the Protocol Layer, Data Link Layer, Channel Allocator, and config-register front-end of the serial link into a new slink_serializer module, exposing a per-channel phy_data_t packet stream (+ TX PHY clock-div/shift config) as its port boundary instead of driving slink_phys_layer directly. slink.sv becomes a thin wrapper pairing slink_serializer with the existing slink_phys_layer generate loop, keeping its external port list and module name unchanged for compatibility with slink_isolate and downstream integrations (e.g. gwaihir). This lets slink_serializer be reused standalone with a different physical/transport backend in another project. Verified: verible-verilog-lint clean; tb_axi_slink (default 1-channel, no channel allocator) and tb_ch_calib_slink (regenerated at 4 channels, exercising the channel-allocator branch) both pass with 0 errors in vsim. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
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August 6, 2026 01:05
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August 6, 2026 08:25
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Split serializer from PHY
This PR introduces an intermediate module,
slink_serializer, which handles converting the AXI protocol into AXI-Stream and splitting the payload into packets.This refactor enables the following:
slink_regout of the serializer allows multiple serializers (and eventually serial links) to be instantiated in the same design, each with its own parametrization. This isn't currently possible: once a downstream project depends on the serial link, IP parameters such asNumChannels,NumLanes, andEnDdrare inherited directly from the generated RDL, tying every instance to the same configuration.