RISC-V CLIC

RISC-V Core Local Interrupt Controller (CLIC) is an interrupt controller for RISC-V cores subsuming the original RISC-V local interrupt scheme (CLINT). It promises pre-emptive, low-latency, vectored, priority/level based interrupts.

This IP is meant to be used together with a suitably modified version of a core. Currently, a modified version of the CV32E40P is supported.

Here is the detailed specification this IP is based on. For the upstream specification visit this link.

Note that this IP is based on an intermediate development version of the CLIC specification which will still change substantially. This IP will try to track the changes of the specification. The specification document in this repository is a snapshot of the upstream specification and the version this IP is based on.

Features

• RISC-V Core Local Interrupt Controller (CLIC) compliant interrupt controller
• Support up to 4096 interrupt lines
• Support up to 8 bits of priority/level information per interrupt line
• Supports (a modified) CV32E40P

Parametrization

Some parameters are configurable. See the marked variables in the table below.

Name             Value Range                   Description
CLICANDBASIC     0-1     (depends on core)     Implements original basic mode also?
CLICPRIVMODES    1-3     (depends on core)     Number privilege modes: 1=M, 2=M/U,
                                                                       3=M/S/U
CLICLEVELS       2-256                         Number of interrupt levels including 0
*NUM_INTERRUPT*  4-4096  (default=256)         Always has MSIP, MTIP, MEIP, CSIP
CLICMAXID        12-4095                       Largest interrupt ID
*CLICINTCTLBITS* 0-8     (default=8)           Number of bits implemented in
                                               clicintctl[i]
CLICCFGMBITS     0-ceil(lg2(CLICPRIVMODES))    Number of bits implemented for
                                               cliccfg.nmbits
CLICCFGLBITS     0-ceil(lg2(CLICLEVELS))       Number of bits implemented for
                                               cliccfg.nlbits
CLICSELHVEC      0-1     (0-1)                 Selective hardware vectoring supported?
CLICMTVECALIGN   6-13    (depends on core)     Number of hardwired-zero least
                                               significant bits in mtvec address.
CLICXNXTI        0-1     (depends on core)     Has xnxti CSR implemented?
CLICXCSW         0-1     (depends on core)     Has xscratchcsw/xscratchcswl
                                               implemented?

Integration and Dependencies

This IP requires

• common_cells
• register_interface

and a suitably modified core (see sections below).

The bender and legacy IPApproX flow are supported.

Besides the native register_interface there is an APB wrapper available.

CLIC and CV32E40P

The patch required to use the CV32E40P together with the CLIC lives in this branch. The CLIC mode is an elaboration time parameter at this moment, but will support a dynamic switch at some point.

Here is the summary

Name             Value
CLICANDBASIC     0   (dynamic mode under development)
CLICPRIVMODES    2
NUM_INTERRUPT    32-256
CLICINTCTLBITS   0-8
CLICSELHVEC      1
CLICMTVECALIGN   8
CLICXNXTI        0   (partial, under development)
CLICXCSW         1

CLIC and CVA6

Not supported yet.

FreeRTOS Support

There is very basic support for the CLIC in pulp-freertos with more a more complete level/priority implementation in the works.

Register interface

The CLIC's register files are generated with regtool and checked into src/, so by default they require no attention of the user.

To regenerate them, go to src/gen/ and call make all with the environment variable REGTOOL pointing to regtool.py of the register_interface repository, e.g.

    make REGTOOL=/path/to/register_interface/vendor/lowrisc_opentitan/util/regtool.py

This generates the SystemVerilog register files and the corresponding C headers from the memory map descriptions in src/gen/*.hjson. Afterwards, make install copies the generated SystemVerilog files into src/, where Bender.yml and src_files.yml pick them up.

Note that the number of interrupt lines is not baked into the generated register files: the CLIC instantiates one register block per interrupt and scales with the N_SOURCE parameter of clic.sv.

Directory Structure

.
├── doc      CLIC spec, Blockdiagrams
├── src      RTL
├── src/gen  Register map descriptions (hjson) and generation Makefile

License

This project uses sourcecode from lowRISC licensed under Apache 2.0. The changes and additions are being made available using Apache 2.0 see LICENSE for more details.