GitHub - notwilliamng/RISC_V: Restricted Instruction Set Computer (V5) OTTER architecture for Xilinx Basys3 Board. Developed using Xilinx Vivado Suite · GitHub

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
ALARM.sv		ALARM.sv
ALU.sv		ALU.sv
BCD.sv		BCD.sv
Branch_Gen.sv		Branch_Gen.sv
CLK_DIV_FS.v		CLK_DIV_FS.v
CSR.sv		CSR.sv
CUDecoder.sv		CUDecoder.sv
CU_FSM.sv		CU_FSM.sv
CathodeDriver.sv		CathodeDriver.sv
Immed_Gen.sv		Immed_Gen.sv
LAB1.sv		LAB1.sv
LAB1_TOP.sv		LAB1_TOP.sv
OTTER_MCU.sv		OTTER_MCU.sv
OTTER_MEM_BYTE.sv		OTTER_MEM_BYTE.sv
OTTER_Wrapper.sv		OTTER_Wrapper.sv
PC.sv		PC.sv
RAM.sv		RAM.sv
RegisterFile.sv		RegisterFile.sv
SONAR.sv		SONAR.sv
SevSegDisp.sv		SevSegDisp.sv
Targ_Gen.sv		Targ_Gen.sv
debounce_one_shot.sv		debounce_one_shot.sv
mux2_1.sv		mux2_1.sv
mux4_1.sv		mux4_1.sv
mux_interupt.sv		mux_interupt.sv
otter_memory.mem		otter_memory.mem

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Restricted Instruction Set Computer (V5) OTTER architecture for Xilinx Basys3 Board. Developed using Xilinx Vivado Suite

basys3-fpga system-verilog xilinx-vivado

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