[dv,sram] add axi_sram verification plan and tag architecture spec - #667
[dv,sram] add axi_sram verification plan and tag architecture spec#667tchilikov-semify wants to merge 4 commits into
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martin-velay
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martin-velay
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I have some comments, and also I'd like to know if you feel it was a bad experience to create a vPlan based on DVPlan? I think you are among th 1st to do the full exercise (except myself) and I need to get feedback 😃
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Thanks for the feedback, @martin-velay 😃 Regarding DVPlan: I found that the flow and working with the tool was actually quite nice and polished (so far). One pain point I have though, is the spec annotation capabilities. A random generated tag means that each time the spec is updated and changed, all of the tags would be re-generated. This would make updating the vplans a bit of a nightmare, since all of the tags would have to be re-mapped. I think a solution to this could be a per-line / per-sentence hash. This way, the hash only changes if the contents of the line change. Of course, this sounds simple but it would introduce edge cases (white spaces, punctuation, etc). I have yet to re-generate or re-map anything, but I anticipate that this would be tedious as it currently stands. Other than this, it was quite straight-forward! I plan to map the actual SV testcases with a comment to the tags as well. |
Thanks @tchilikov-semify for the feedback. |
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marnovandermaas
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marnovandermaas
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I've left some reviews on the initial commits (the vplan I'll leave to @martin-velay
| # rdl: embed the memory map table into the architecture document | ||
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| "util/rdlgenerator.py", | ||
| "embed-memory-map-md", |
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I would probably replace the image generation with the markdown generation here so we don't have two very similar processes in the codebase.
| MEMORY_MAP_MD_END = "<!-- END generated memory map -->" | ||
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| def memory_map_table(rdljson: dict) -> list[str]: |
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This dict doesn't have the sub-types. You can check you've done this correctly using mypy.
| If a portion of the 128-bit aligned region is written it must clear the tag for the whole region including when a partial write strobe is used.<!-- 893tz4 --> | ||
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| Reads that only read part of a 64-bit value are allowed from valid capability regions, but these should have their tag cleared.<!-- raa5pw --> | ||
| Reads that only read part of a 64-bit value are allowed from valid capability regions, but these reads should have their tag cleared in the response. These reads do not modify the state of the tag in memory.<!-- raa5pw --> |
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Each sentence should have its own line.
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