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intel/systemc-compiler

Intel® Compiler for SystemC*

*Other names and brands may be claimed as the property of others.

Introduction

The SystemC Compiler (ICSC) translates synthesizable SystemC design into equivalent SystemVerilog code.

The SystemC Compiler checks a SystemC design for common coding mistakes and generates human-readable SystemVerilog code. The Compiler supports SystemC synthesizable subset in method and thread processes, and arbitrary C++ code in module constructors. ICSC is based on Clang/LLVM 18.1.8, supports C++ 11/14/17/20 standards and includes SystemC 3.0.1.

See more information at Intel Compiler for SystemC wiki.

Common SystemC Library

Common SystemC Library consists of types, modules and functions which could be used in SystemC designs and testbench code. All the components are synthesizable with the SystemC Compiler. Common SystemC Library has three parts:

AI support

The SystemC Compiler and Common SystemC Library semantics, rules, and restrictions are supported with Agent Skills.

The skills are based on several Basic documents, ICSC unit tests, designs and examples. We are actively using the the skills for our SystemC designs.

Getting started

The SystemC Compiler can be installed at most Linux and Windows Subsystem for Linux (WSL). There is install.sh script that downloads and builds the compiler and the required dependencies at Ubuntu 24.04, Ubuntu 22.04, Ubuntu 20.04, SLES15, SLES12 and others.

An instruction how to install and run ISCS is given at Getting started.

Documentation

User guide document describes installation procedure, run tool options, preparation of SystemC design for synthesis, tool extensions and advanced verification features.

The SystemC Compiler supports SystemC Synthesizable Subset. Details of SystemC/C++ subset supported are described at SystemC/C++ supported.

Publications

License

ICSC is distributed under the Apache License v2.0 with LLVM Exceptions.

Help

To get help please submit your question or issue

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This tool translates synthesizable SystemC code to synthesizable SystemVerilog.

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