[libspirv] Use clc unary relational functions#22144
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Also cherry-picks 9cc6c93 to avoid SignBitSet regression. IsNormal and SignBitSet are now vectorized. NFC to other built-ins. in function _Z16__spirv_IsNormalDv2_f: > %2 = extractelement <2 x float> %0, i64 0 > %3 = tail call noundef i1 @llvm.is.fpclass.f32(float %2, i32 264) > %4 = zext i1 %3 to i8 > %5 = insertelement <2 x i8> poison, i8 %4, i64 0 > %6 = extractelement <2 x float> %0, i64 1 > %7 = tail call noundef i1 @llvm.is.fpclass.f32(float %6, i32 264) > %8 = zext i1 %7 to i8 > %9 = insertelement <2 x i8> %5, i8 %8, i64 1 > %10 = icmp ne <2 x i8> %9, zeroinitializer > %11 = sext <2 x i1> %10 to <2 x i8> < %2 = tail call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %0, i32 264) < %3 = sext <2 x i1> %2 to <2 x i8> in function _Z18__spirv_SignBitSetDv2_Dh: > %3 = extractelement <2 x i16> %2, i64 0 > %4 = lshr i16 %3, 15 > %5 = trunc nuw nsw i16 %4 to i8 > %6 = insertelement <2 x i8> poison, i8 %5, i64 0 > %7 = extractelement <2 x i16> %2, i64 1 > %8 = lshr i16 %7, 15 > %9 = trunc nuw nsw i16 %8 to i8 > %10 = insertelement <2 x i8> %6, i8 %9, i64 1 > %11 = icmp ne <2 x i8> %10, zeroinitializer > %12 = sext <2 x i1> %11 to <2 x i8> < %3 = ashr <2 x i16> %2, splat (i16 15) < %4 = trunc nsw <2 x i16> %3 to <2 x i8>
bratpiorka
approved these changes
May 29, 2026
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Also cherry-picks llvm/llvm-project@9cc6c9375faa to avoid SignBitSet regression.
IsNormal and SignBitSet are now vectorized. NFC to other built-ins. in function _Z16__spirv_IsNormalDv2_f:
> %2 = extractelement <2 x float> %0, i64 0
> %3 = tail call noundef i1 @llvm.is.fpclass.f32(float %2, i32 264)
> %4 = zext i1 %3 to i8
> %5 = insertelement <2 x i8> poison, i8 %4, i64 0
> %6 = extractelement <2 x float> %0, i64 1
> %7 = tail call noundef i1 @llvm.is.fpclass.f32(float %6, i32 264)
> %8 = zext i1 %7 to i8
> %9 = insertelement <2 x i8> %5, i8 %8, i64 1
> %10 = icmp ne <2 x i8> %9, zeroinitializer
> %11 = sext <2 x i1> %10 to <2 x i8>
< %2 = tail call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %0, i32 264)
< %3 = sext <2 x i1> %2 to <2 x i8>
in function _Z18__spirv_SignBitSetDv2_Dh:
> %3 = extractelement <2 x i16> %2, i64 0
> %4 = lshr i16 %3, 15
> %5 = trunc nuw nsw i16 %4 to i8
> %6 = insertelement <2 x i8> poison, i8 %5, i64 0
> %7 = extractelement <2 x i16> %2, i64 1
> %8 = lshr i16 %7, 15
> %9 = trunc nuw nsw i16 %8 to i8
> %10 = insertelement <2 x i8> %6, i8 %9, i64 1
> %11 = icmp ne <2 x i8> %10, zeroinitializer
> %12 = sext <2 x i1> %11 to <2 x i8>
< %3 = ashr <2 x i16> %2, splat (i16 15)
< %4 = trunc nsw <2 x i16> %3 to <2 x i8>