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Add XPU expected slice for SlowBnb4BitFluxControlWithLoraTests::test_lora_loading#14202

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Add XPU expected slice for SlowBnb4BitFluxControlWithLoraTests::test_lora_loading#14202
jiqing-feng wants to merge 1 commit into
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jiqing-feng:xpu_int8

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@jiqing-feng

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What

Add a device-specific expected output slice for the Flux Control LoRA bitsandbytes
test so it passes on Intel XPU, while keeping the original CUDA reference values as
the default.

Why

SlowBnb4BitFluxControlWithLoraTests::test_lora_loading fails on XPU with a large
mismatch (cosine distance ≈ 0.044 vs the 1e-3 threshold):

out_slice=array([0.0955, 0.1223, 0.1509, 0.0872, 0.1155, 0.1890, 0.0754, 0.1028, 0.2178])
expected_slice=array([0.2029, 0.2136, 0.2268, 0.1921, 0.1997, 0.2185, 0.2021, 0.2183, 0.2292])

Root cause is not a bitsandbytes XPU bug. Direct probes show the bnb int8 path is
aligned across backends:

  • int8 dequantize (int8_vectorwise_dequant): XPU vs CPU identical (rel 6.96e-03, just the normal quantization error).
  • int8 matmul (Linear8bitLt): XPU vs CPU rel 1.99e-06 (pure floating-point noise).

The hard-coded expected_slice was recorded on CUDA, and 1e-3 is too tight to be
portable across accelerators — even the plain no-LoRA test_quality drifts to
~0.0039 on XPU. This test is affected the most because loading the Control LoRA
dequantizes and expands the quantized x_embedder (the first projection into the
transformer), and that difference accumulates over the 8 denoising steps.

Change

  • Import Expectations in tests/quantization/bnb/test_mixed_int8.py.
  • Store the reference slice per backend via Expectations:
    • (None, None): unchanged original CUDA values (default for all non-XPU hardware).
    • ("xpu", 5): newly recorded XPU reference values.

The 1e-3 threshold is unchanged, and CUDA/other backends keep the exact original
behavior.

Testing

RUN_SLOW=1 python -m pytest \
  tests/quantization/bnb/test_mixed_int8.py::SlowBnb4BitFluxControlWithLoraTests::test_lora_loading
# 1 passed

@github-actions github-actions Bot added size/S PR with diff < 50 LOC tests labels Jul 16, 2026
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Hi @jiqing-feng, thanks for the PR! It does not appear to link an issue it fixes. If this PR addresses an existing issue, please add a closing keyword (e.g. Fixes #1234) to the PR description so the issue is linked. See the contribution guide for more details. If this PR intentionally does not fix a tracked issue, a maintainer can add the no-issue-needed label to silence this reminder.

@jiqing-feng

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This PR doesn't fix a tracked issue — it only adds a device-specific expected_slice so SlowBnb4BitFluxControlWithLoraTests::test_lora_loading passes on Intel XPU, while keeping the original CUDA reference values unchanged.

Signed-off-by: jiqing-feng <jiqing.feng@intel.com>
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