feat: FPGA VANC timecode inserter for Ninja V recording trigger

[alfskaar]

Summary

Sample Verilog module and documentation for injecting SMPTE 12M-2 timecode as VANC (Vertical Ancillary Data) packets into the HDMI video blanking interval.

Background

The Atomos Ninja V "HDMI Device" trigger modes (Canon EOS R, Sony ILCE-7SM3, etc.) use VANC timecode — not HDMI InfoFrames — to detect recording state.

HDfury captures of a real Canon EOS R confirmed all InfoFrames are byte-for-byte identical between REC ON and REC OFF. The trigger mechanism is SMPTE 12M-2 timecode embedded at the pixel level during vertical blanking.

The IT66121 HDMI transmitter cannot inject VANC — it only handles InfoFrames and audio. VANC must be injected by the FPGA before the video reaches the IT66121.

Files

File	Description
fpga_vanc_timecode/vanc_timecode_inserter.v	8-bit DE-based Verilog module: line/pixel counters, SMPTE ST 291M packet builder with BCD timecode, timecode input latching, DE-guard abort, insertion state machine, video passthrough mux
fpga_vanc_timecode/README.md	VANC packet format spec (SMPTE ST 291M / 12M-2), integration notes, blanking line selection, horizontal position guidance, CPU register interface

Integration

Camera RX → Frame Buffer → Scaler → [VANC Inserter] → IT66121 Parallel Input

CPU (ARM / Allwinner V536) controls timecode via FPGA registers:

• TC_HOURS, TC_MINUTES, TC_SECONDS, TC_FRAMES, TC_ENABLE
• ARM increments timecode once per second; FPGA inserts VANC packets every frame

Status

Sample/reference code for FPGA integration. Software-side Canon EOS R VSIF trigger code exists separately in the firmware (not included in this PR).

[Copilot]

Pull request overview

Adds a reference FPGA implementation and accompanying documentation for injecting SMPTE 12M-2 timecode as SMPTE ST 291M VANC packets into the HDMI video vertical blanking interval, enabling Atomos Ninja V “HDMI Device” record trigger behavior.

Changes:

• Introduces a Verilog VANC timecode inserter module for an 8-bit DE-based video interface (with packet builder + insertion FSM).
• Documents the VANC packet structure, integration placement, and recommended blanking line / horizontal offset guidance.

Reviewed changes

Copilot reviewed 2 out of 2 changed files in this pull request and generated 4 comments.

File	Description
fpga_vanc_timecode/vanc_timecode_inserter.v	Implements line/pixel counting, timecode latching, ST 291M packet construction, and blanking-safe insertion mux.
fpga_vanc_timecode/README.md	Explains Ninja V trigger mechanism and provides packet format + integration notes for the sample module.

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