Verilog: import of tasks/functions in interfaces and modports - #2115
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Verilog: import of tasks/functions in interfaces and modports#2115kroening wants to merge 1 commit into
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Fix the two frontend bugs documented as KNOWNBUG by PR #2113 and flip both tests to CORE. modport_import1: IEEE 1800-2017 25.7 allows a modport to import interface tasks/functions via 'import' in the modport item list. The parser rejected this with 'syntax error, unexpected import'. Add modport_tf_port and the import/export alternatives to modport_ports_declaration. package_import1: a package import inside an interface body (IEEE 1800-2017 26.3) made imported typedefs visible but calling an imported function failed with 'unknown function'. convert_expr_function_call ignored the import and preresolved attributes that scanner.l attaches to identifiers; consult them before falling back to module/unit scope.
kroening
marked this pull request as draft
August 21, 2026 18:55
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Fixes the two frontend bugs documented as KNOWNBUG by #2113 and flips both tests to CORE.
interface/modport_import1— parser (IEEE 1800-2017 §25.7)A modport may import interface tasks/functions via
importin the modport item list. The parser rejected this withsyntax error, unexpected import. Adds amodport_tf_portrule (method_prototype | tf_identifier) plusimport/exportalternatives tomodport_ports_declaration, with two new IREP IDs (verilog_modport_import/verilog_modport_export). No new grammar conflicts.interface/package_import1— elaboration (IEEE 1800-2017 §26.3)A package import inside an interface body made imported typedefs visible, but calling an imported function failed with
unknown function.convert_expr_function_callresolved the callee only in module and compilation-unit scope, ignoring theimport/preresolvedattributes thatscanner.lalready attaches to imported identifiers. It now consults those attributes first (mirroringconvert_verilog_identifier) before the module/unit fallback. This also fixes the same call form in modules.Testing
make -C srcbuilds clean.make -C regression/verilog testpasses;modport_import1andpackage_import1now run as OK (previously SKIPPED as KNOWNBUG), and nothing else regressed.no properties/EXIT=10; the must-not-match blocks (syntax error,CONVERSION ERROR) no longer appear, so each flips from KNOWNBUG to CORE, following theelsif3precedent (Verilog: fix elsif-chain dual-emission in preprocessor #2112).