x86: use effective address size for the loop counter register - #3025
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x86: use effective address size for the loop counter register#3025phverg wants to merge 1 commit into
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The implicit counter register of loop/loope/loopne (and its regs_read/ regs_write detail) was chosen from the CPU mode alone (CX/ECX/RCX for 16/32/64-bit), ignoring a 0x67 address-size prefix. In 64-bit mode `67 e2 c2` (loop) therefore reported rcx instead of ecx. Select the counter register from the effective address size (insn->detail->x86.addr_size), which the 0x67 prefix already accounts for, while the instruction-pointer register keeps following the mode. Fixes capstone-engine#2823
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@hainest Would you mind taking a look? |
Rot127
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Aug 12, 2026
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Fixes #2823.
The implicit counter register of
loop/loope/loopne(and itsregs_read/regs_writedetail) was selected from the CPU mode alone (CX/ECX/RCX for 16/32/64-bit), ignoring a0x67address-size prefix. The loop counter register is chosen by the effective address size, so67 e2 c2(loop) in 64-bit mode reportedrcxinstead ofecx.This selects the counter register from the effective address size (
insn->detail->x86.addr_size, which the0x67prefix already accounts for), while the instruction-pointer register keeps following the mode.Before:
After:
The fix also corrects the 16-bit and 32-bit cases where
0x67changes the effective address size (16-bit +0x67→ ECX, 32-bit +0x67→ CX). The three affectedtests/details/x86.yamlfixtures (which carried# BUG: should be ecxmarkers) are updated toecx, andcstestpasses (40/40 cases).