Skip to content

fix(thumb): keep SP 8-byte aligned for native calls with >4 argv words #5007

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
SupposedlySam wants to merge 1 commit into
base: main
Choose a base branch
from
+6 −2
Open

fix(thumb): keep SP 8-byte aligned for native calls with >4 argv words #5007

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 6 additions & 2 deletions core/iwasm/common/arch/invokeNative_thumb.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -61,12 +61,16 @@ _invokeNative:

sub r5, r5, #4 /* argc -= 4, now we have r0 ~ r3 */

/* Ensure address is 8 byte aligned */
/* Reserve stack for the remaining args, rounded up to 8 bytes so SP
stays 8-byte aligned at the blx below (AAPCS requires 8-byte SP
alignment at a public interface). SP is already 8-aligned here:
the prologue pushed r4-r7 + lr (20 bytes) and did sub sp,#4, i.e.
24 bytes (see .cfi_def_cfa_offset 24). The reservation must
therefore be a multiple of 8 and nothing more. */
lsl r6, r5, #2 /* r6 = argc * 4 */
mov r7, #7
add r6, r6, r7 /* r6 = (r6 + 7) & ~7 */
bic r6, r6, r7
add r6, r6, #4 /* +4 because odd(5) registers are in stack */
mov r7, sp
sub r7, r7, r6 /* reserved stack space for left arguments */
mov sp, r7
Expand Down
Loading