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aot: pin host CPU features for the default native target (fix SIGILL on AVX-512-masked runners) #4998

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Merged
lum1n0us merged 1 commit into from
Jul 24, 2026
+13 −1
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aot: pin host CPU features for the default native target (fix SIGILL on AVX-512-masked runners) #4998

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14 changes: 13 additions & 1 deletion core/iwasm/compilation/aot_llvm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2632,7 +2632,7 @@ aot_create_comp_context(const AOTCompData *comp_data, aot_comp_option_t option)
LLVMTargetRef target;
char *triple = NULL, *triple_norm, *arch, *abi;
char *cpu = NULL, *features, buf[128];
char *triple_norm_new = NULL, *cpu_new = NULL;
char *triple_norm_new = NULL, *cpu_new = NULL, *features_new = NULL;
char *err = NULL, *fp_round = "round.tonearest",
*fp_exce = "fpexcept.strict";
char triple_buf[128] = { 0 }, features_buf[128] = { 0 };
Expand Down Expand Up @@ -3115,6 +3115,15 @@ aot_create_comp_context(const AOTCompData *comp_data, aot_comp_option_t option)
aot_set_last_error("llvm get host cpu name failed.");
goto fail;
}
/* Also pin the host CPU's actually-enabled features. The CPU name
* alone (e.g. "znver4") makes LLVM enable every feature that model
* implies, including AVX-512; but a virtualized host can have those
* masked out of cpuid, so without the real feature string the AOT
* code may emit instructions the running CPU rejects with SIGILL.
* LLVMGetHostCPUFeatures() reflects what is actually enabled, and
* this mirrors the JIT target-machine setup. */
if (!features)
features = features_new = LLVMGetHostCPUFeatures();
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}
else if (triple) {
/* Normalize a target triple */
Expand Down Expand Up @@ -3500,6 +3509,9 @@ aot_create_comp_context(const AOTCompData *comp_data, aot_comp_option_t option)
if (cpu_new)
LLVMDisposeMessage(cpu_new);

if (features_new)
LLVMDisposeMessage(features_new);

if (!ret)
aot_destroy_comp_context(comp_ctx);

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