All pull requests

Pull requests

• [Relax][ONNX] Support Call and Var sequence expressions in sequence operators

  #20964·Chaitanya140904 opened Nov 10, 2026·

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• [Relax][ONNX] Fix default direction attribute decoding in BitShift

  #20963·Chaitanya140904 opened Nov 10, 2026·

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• [Fix][DLight] Fall back when matmul epilogues cannot be inlined

  #20957·wawahejun opened Nov 10, 2026·

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• [FIX][S-TIR] Bind merged shared memory sizes before the merged allocation

  #20955·JonSnow1807 opened Nov 9, 2026·

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• [FIX][S-TIR] Do not reverse-inline a computing consumer into a block with init

  #20954·JonSnow1807 opened Nov 9, 2026·

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• [Relax][Frontend][ONNX] Add QLinearConv operator converter

  #20953·Chaitanya140904 opened Nov 9, 2026·

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• [Relax][Frontend][ONNX] Add DFT operator converter

  #20952·Chaitanya140904 opened Nov 9, 2026·

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• [Relax][Frontend][ONNX] Add QLinearMatMul operator converter

  #20951·Chaitanya140904 opened Nov 9, 2026·

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• [Relax][TVMScript] Keep metadata for bare constant If-branch bodies

  #20946·cchung100m opened Nov 9, 2026Contributor·

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• [Fix][Relax][Frontend][Torch] Accept a Python scalar source in copy_

  #20945·sohailshk opened Nov 9, 2026·

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• [Fix][Relax][Frontend][Torch] Clamp negative slice_scatter bounds to the start of the dimension

  #20944·sohailshk opened Nov 9, 2026·

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• [Typo] The beginning of scope should be accociated with offset > 0

  #20938·y1lan opened Nov 8, 2026·

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• [Relax][ONNX] Add CumProd operator support

  #20937·Anirudh-65 opened Nov 8, 2026Contributor·

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• [Fix][Relax] Preserve FP32 normalization in FP16 LayerNorm decomposition

  #20930·zzznnn-1 opened Nov 7, 2026·

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• [DOCS] Replace stale Python module paths after the TIRx extraction

  #20929·erhsh opened Nov 7, 2026Contributor·2 tasks done·

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• [Relax][PyTorch] Support Tensor.t in the FX importer

  #20927·tandede opened Nov 7, 2026Contributor·

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• [Fix][Relax] Dispatch median sorting on GPU

  #20917·0z5a opened Nov 4, 2026·

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• [Fix][Relax] Preserve global median keepdims shape

  #20916·0z5a opened Nov 4, 2026·

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• [TIR][CUDA] Require aligned addresses for cp.async

  #20913·0z5a opened Nov 4, 2026·

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• [TIR][CUDA] Avoid cp.async for noncontiguous vector copies

  #20911·0z5a opened Nov 4, 2026·

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• [Fix][Relax][ONNX] Convert OneHot depth to int

  #20908·tandede opened Nov 4, 2026Contributor·

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• [Perf][Relax] Skip future KV tiles in causal ragged prefill

  #20903·dotcom07 opened Nov 3, 2026·

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• [Fix][Relax][PyTorch] Handle one-sided clamp on integer tensors

  #20885·JakkulaVeerababu opened Nov 2, 2026·

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• [Relax][Frontend][ONNX] Support zero-length outputs in Split

  #20862·dundysm opened Oct 31, 2026·

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• [Relax][Frontend][ONNX] Lower ThresholdedRelu with where in the input dtype

  #20861·dundysm opened Oct 31, 2026·

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