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26 changes: 22 additions & 4 deletions doc/admin-guide/files/records.yaml.en.rst
Original file line number Diff line number Diff line change
Expand Up @@ -2892,10 +2892,28 @@ RAM Cache

.. ts:cv:: CONFIG proxy.config.cache.ram_cache.algorithm INT 1

Two distinct RAM caches are supported, the default (1) being the simpler
**LRU** (*Least Recently Used*) cache. As an alternative, the **CLFUS**
(*Clocked Least Frequently Used by Size*) is also available, by changing this
configuration to 0.
Three RAM cache eviction algorithms are supported, selected by this value:

``1``
**LRU** (*Least Recently Used*), the default -- the simplest policy,
favoring recency. Pairs with
:ts:cv:`proxy.config.cache.ram_cache.use_seen_filter` for scan
resistance.

``0``
**CLFUS** (*Clocked Least Frequently Used by Size*), which balances
recency, frequency, and object size. It is the only algorithm that
supports in-RAM compression
(:ts:cv:`proxy.config.cache.ram_cache.compress`).

``2``
**S3-FIFO** (*Simple Scalable Static FIFO*): a small admission queue and
a main queue (both FIFO), plus a ghost queue of recently evicted keys,
which together filter one-hit-wonders. Scan-resistant and inexpensive
(no per-hit reordering); strong hit rates on CDN and key-value
workloads. Its eviction metadata (including the ghost) is accounted
within :ts:cv:`proxy.config.cache.ram_cache.size`. Experimental; it does
not use the seen filter or support in-RAM compression.

.. ts:cv:: CONFIG proxy.config.cache.ram_cache.use_seen_filter INT 1

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14 changes: 9 additions & 5 deletions doc/admin-guide/storage/index.en.rst
Original file line number Diff line number Diff line change
Expand Up @@ -75,18 +75,22 @@ and reduces load on disks, especially during temporary traffic peaks.
You can configure the RAM cache size to suit your needs, as described in
:ref:`changing-the-size-of-the-ram-cache` below.

The RAM cache supports two cache eviction algorithms, a regular *LRU*
(Least Recently Used) and the more advanced *CLFUS* (Clocked Least
The RAM cache supports three cache eviction algorithms: a regular *LRU*
(Least Recently Used); the more advanced *CLFUS* (Clocked Least
Frequently Used by Size; which balances recentness, frequency, and size
to maximize hit rate, similar to a most frequently used algorithm).
The default is to use *LRU*, and this is controlled via
to maximize hit rate, similar to a most frequently used algorithm); and
*S3-FIFO* (Simple Scalable Static FIFO), a FIFO-based policy whose small
admission queue and ghost list filter one-hit-wonders, giving strong hit
rates on CDN and key-value workloads at low cost. The default is to use
*LRU*, and this is controlled via
:ts:cv:`proxy.config.cache.ram_cache.algorithm`.

Both the *LRU* and *CLFUS* RAM caches support a configuration to increase
scan resistance. In a typical *LRU*, if you request all possible objects in
sequence, you will effectively churn the cache on every request. The option
:ts:cv:`proxy.config.cache.ram_cache.use_seen_filter` can be set to add some
resistance against this problem.
resistance against this problem. *S3-FIFO* is scan-resistant by design,
through its admission queue, and does not use the seen filter.

In addition, *CLFUS* also supports compressing in the RAM cache itself.
This can be useful for content which is not compressed by itself (e.g.
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5 changes: 3 additions & 2 deletions include/iocore/cache/Cache.h
Original file line number Diff line number Diff line change
Expand Up @@ -36,8 +36,9 @@ static constexpr ts::ModuleVersion CACHE_MODULE_VERSION(1, 0);

#define SCAN_KB_PER_SECOND 8192 // 1TB/8MB = 131072 = 36 HOURS to scan a TB

#define RAM_CACHE_ALGORITHM_CLFUS 0
#define RAM_CACHE_ALGORITHM_LRU 1
#define RAM_CACHE_ALGORITHM_CLFUS 0
#define RAM_CACHE_ALGORITHM_LRU 1
#define RAM_CACHE_ALGORITHM_S3FIFO 2

#define CACHE_COMPRESSION_NONE 0
#define CACHE_COMPRESSION_FASTLZ 1
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1 change: 1 addition & 0 deletions include/iocore/eventsystem/Thread.h
Original file line number Diff line number Diff line change
Expand Up @@ -134,6 +134,7 @@ class Thread
ProxyAllocator openDirEntryAllocator;
ProxyAllocator ramCacheCLFUSEntryAllocator;
ProxyAllocator ramCacheLRUEntryAllocator;
ProxyAllocator ramCacheS3FIFOEntryAllocator;
ProxyAllocator evacuationBlockAllocator;
ProxyAllocator ioDataAllocator;
ProxyAllocator ioAllocator;
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1 change: 1 addition & 0 deletions src/iocore/cache/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,7 @@ add_library(
PreservationTable.cc
RamCacheCLFUS.cc
RamCacheLRU.cc
RamCacheS3FIFO.cc
Store.cc
Stripe.cc
StripeSM.cc
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7 changes: 7 additions & 0 deletions src/iocore/cache/CacheProcessor.cc
Original file line number Diff line number Diff line change
Expand Up @@ -1486,6 +1486,10 @@ CacheProcessor::cacheInitialized()

if (gnstripes) {
// new ram_caches, with algorithm from the config
static const char *const ram_cache_algorithm_name[] = {"CLFUS", "LRU", "S3-FIFO"};
int const ram_alg = cache_config_ram_cache_algorithm;
Dbg(dbg_ctl_cache_init, "ram_cache algorithm = %d (%s)", ram_alg,
(ram_alg >= 0 && ram_alg <= RAM_CACHE_ALGORITHM_S3FIFO) ? ram_cache_algorithm_name[ram_alg] : "unknown");
for (int i = 0; i < gnstripes; i++) {
switch (cache_config_ram_cache_algorithm) {
default:
Expand All @@ -1495,6 +1499,9 @@ CacheProcessor::cacheInitialized()
case RAM_CACHE_ALGORITHM_LRU:
gstripes[i]->ram_cache = new_RamCacheLRU();
break;
case RAM_CACHE_ALGORITHM_S3FIFO:
gstripes[i]->ram_cache = new_RamCacheS3FIFO();
break;
}
}

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3 changes: 2 additions & 1 deletion src/iocore/cache/CacheTest.cc
Original file line number Diff line number Diff line change
Expand Up @@ -679,7 +679,8 @@ REGRESSION_TEST(ram_cache)(RegressionTest *t, int level, int *pstatus)
for (int s = 20; s <= 24; s += 4) {
int64_t cache_size = 1LL << s;
*pstatus = REGRESSION_TEST_PASSED;
if (!test_RamCache(t, new_RamCacheLRU(), "LRU", cache_size) || !test_RamCache(t, new_RamCacheCLFUS(), "CLFUS", cache_size)) {
if (!test_RamCache(t, new_RamCacheLRU(), "LRU", cache_size) || !test_RamCache(t, new_RamCacheCLFUS(), "CLFUS", cache_size) ||
!test_RamCache(t, new_RamCacheS3FIFO(), "S3-FIFO", cache_size)) {
*pstatus = REGRESSION_TEST_FAILED;
}
}
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1 change: 1 addition & 0 deletions src/iocore/cache/P_RamCache.h
Original file line number Diff line number Diff line change
Expand Up @@ -45,3 +45,4 @@ class RamCache

RamCache *new_RamCacheLRU();
RamCache *new_RamCacheCLFUS();
RamCache *new_RamCacheS3FIFO();
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