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RISCV: Zicond extension - #35

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mananni-silabs wants to merge 1 commit into
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SiliconLabsSoftware:feature/RISCV_Zicond_extension
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RISCV: Zicond extension#35
mananni-silabs wants to merge 1 commit into
antmicro:masterfrom
SiliconLabsSoftware:feature/RISCV_Zicond_extension

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Add support for the two Zicond instructions:

  • czero.eqz rd, rs1, rs2 - rd = (rs2 == 0) ? 0 : rs1
  • czero.nez rd, rs1, rs2 - rd = (rs2 != 0) ? 0 : rs1

Add support for the two Zicond instructions:
- czero.eqz rd, rs1, rs2 - rd = (rs2 == 0) ? 0 : rs1
- czero.nez rd, rs1, rs2 - rd = (rs2 != 0) ? 0 : rs1
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