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adithyarg/README.md

Hi, I’m Adithya

Electronics Engineer

Github LinkedIn Gmail


About Me

  • Enjoy building systems that connect hardware with code
  • Open to learning and collaboration
  • Reach me at: adithyarg14@gmail.com

Languages & Tools


Focus Areas

  • Digital Logic & RTL Concepts
  • Embedded Firmware & Protocols (I2C/UART/SPI)
  • Automation with Python
  • Debugging and system bring-up

“Logic first, tools next.”

Pinned Loading

  1. MLP-Accelerator-for-MNIST-on-Basys3-FPGA MLP-Accelerator-for-MNIST-on-Basys3-FPGA Public

    An FPGA-based neural network inference accelerator built on the Digilent Basys3 (Artix-7 XC7A35T) using Verilog and Vivado. The design classifies handwritten MNIST digits (0–9) with ~94% accuracy u…

    Verilog

  2. ImageProcessing-Verilog ImageProcessing-Verilog Public

    Hardware-based image processing system implemented in Verilog with supporting Python scripts for handling .bmp ↔ .mem conversions. Supports both basic pixel filters (invert, grayscale, brightness, …

    Verilog

  3. NeuralEdge NeuralEdge Public

    NeuralEdge is an FPGA-based AI co-processor for real-time neural network inference on embedded systems. Built on the Digilent Basys3 (Artix-7), it accelerates quantized MLP inference for applicatio…

    Python 1

  4. RV32I-5Stage-Pipeline-Processor RV32I-5Stage-Pipeline-Processor Public

    A complete RISC-V RV32I 5-stage pipelined processor in Verilog. Implements full RV32I ISA with data forwarding, load-use hazard detection, and branch/jump flush. Simulated and verified in Vivado 20…

    Verilog

  5. samsung-riscv samsung-riscv Public

    RISC-V Talent Development Program, powered by Samsung Semiconductor India Research (SSIR) along with VLSI System Design (VSD)

  6. amanbangeraa/CashCue amanbangeraa/CashCue Public

    TypeScript