VMM: AVIC work-in-progress

include/VBox/err.h

@@ -3143,6 +3143,10 @@
 #define VERR_APIC_IPE_1                             (-6706)
 /** APIC internal error \#2. */
 #define VERR_APIC_IPE_2                             (-6707)
+/** Update the APIC state in R3 after an unaccelerated write (AVIC/APICv). */
+#define VINF_APIC_R3_UPDATE_STATE                   6708
+/** Pending interrupt deferred for delivery by hardware (AVIC/APICv). */
+#define VERR_APIC_INTR_DEFER                        (-6709)
 /** @} */
 
 /** @name NEM Status Codes

include/VBox/vmm/hm.h

@@ -300,6 +300,7 @@ VMMR3DECL(bool)                 HMR3IsEnabled(PUVM pUVM);
 VMMR3DECL(bool)                 HMR3IsNestedPagingActive(PUVM pUVM);
 VMMR3DECL(bool)                 HMR3AreVirtApicRegsEnabled(PUVM pUVM);
 VMMR3DECL(bool)                 HMR3IsPostedIntrsEnabled(PUVM pUVM);
+VMMR3DECL(bool)                 HMR3IsAvicEnabled(PUVM pUVM);
 VMMR3DECL(bool)                 HMR3IsVpidActive(PUVM pUVM);
 VMMR3DECL(bool)                 HMR3IsUXActive(PUVM pUVM);
 VMMR3DECL(bool)                 HMR3IsSvmEnabled(PUVM pUVM);

include/VBox/vmm/hm_svm.h

@@ -65,6 +65,8 @@
 #define SVM_MSRPM_PAGES                 2
 /** Number of pages required for the IO permission bitmap. */
 #define SVM_IOPM_PAGES                  3
+/** Number of pages required for the AVIC per-VM (APIC access, logical, physical tables). */
+#define SVM_AVIC_PAGES                  3
 /** @} */
 
 /*
@@ -337,6 +339,20 @@
 #endif /* !IN_REM_R3*/
 
 
+/** @name SVMVMCB.u64ExitInfo2 for AVIC Incomplete IPI.
+ * @{
+ */
+#define SVM_EXIT2_INC_IPI_INDEX_MASK                UINT64_C(0xfff)
+#define SVM_EXIT2_INC_IPI_ID_SHIFT                  32
+#define SVM_EXIT2_INC_IPI_INDEX_INVALID_INTR_TYPE   0
+#define SVM_EXIT2_INC_IPI_INDEX_TARGET_NOT_RUNNING  1
+#define SVM_EXIT2_INC_IPI_INDEX_INVALID_TARGET      2
+#define SVM_EXIT2_INC_IPI_INDEX_INVALID_PTR         3
+#define SVM_EXIT2_INC_IPI_INDEX_INVALID_IPI_VECTOR  4
+#define SVM_EXIT2_INC_IPI_INDEX_UNACCEL_IPI         5
+/** @} */
+
+
 /** @name SVMVMCB.u64ExitInfo2 for task switches
  * @{
  */
@@ -627,7 +643,8 @@ typedef union
         uint32_t    u3Reserved          : 3;
         uint32_t    u1VIntrMasking      : 1;    /* V_INTR_MASKING */
         uint32_t    u1VGifEnable        : 1;    /* VGIF enable */
-        uint32_t    u5Reserved          : 5;
+        uint32_t    u4Reserved          : 4;
+        uint32_t    u1X2AvicEnable      : 1;    /* X2AVIC enable */
         uint32_t    u1AvicEnable        : 1;    /* AVIC enable */
         uint32_t    u8VIntrVector       : 8;    /* V_INTR_VECTOR */
         uint32_t    u24Reserved         : 24;

include/VBox/vmm/pdmapic.h

@@ -362,6 +362,26 @@ typedef struct PDMAPICBACKENDR3
      */
     DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnExportState, (PVMCPUCC pVCpu));
 
+    /**
+     * Updates the APIC state after a write to the APIC page by hardware.
+     *
+     * @returns Strict VBox status code.
+     * @param   pVCpu   The cross context virtual CPU structure.
+     *
+     * @note This is a helper for AVIC/APICv when used on AMD or Intel.
+     */
+    DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnUpdateStateAfterWrite, (PVMCPUCC pVCpu, uint16_t offApicReg));
+
+    /**
+     * Sets the End-Of-Interrupt (EOI) register when the vector corresponding
+     * to the EOI is given.
+     *
+     * @returns Strict VBox status code.
+     * @param   pVCpu       The cross context virtual CPU structure.
+     * @param   uVector     The vector for the attempted EOI.
+     */
+    DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiFast, (PVMCPUCC pVCpu, uint8_t uVector));
+
     /** @name Reserved for future (MBZ).
      * @{ */
     DECLR3CALLBACKMEMBER(int, pfnReserved0, (void));
@@ -370,8 +390,6 @@ typedef struct PDMAPICBACKENDR3
     DECLR3CALLBACKMEMBER(int, pfnReserved3, (void));
     DECLR3CALLBACKMEMBER(int, pfnReserved4, (void));
     DECLR3CALLBACKMEMBER(int, pfnReserved5, (void));
-    DECLR3CALLBACKMEMBER(int, pfnReserved6, (void));
-    DECLR3CALLBACKMEMBER(int, pfnReserved7, (void));
     /** @} */
 } PDMAPICBACKENDR3;
 /** Pointer to ring-3 APIC backend. */
@@ -624,10 +642,31 @@ typedef struct PDMAPICBACKENDR0
      * Exports the APIC state.
      *
      * @returns Strict VBox status code.
-     * @param   pVCpu   The cross context virtual CPU structure.
+     * @param   pVCpu           The cross context virtual CPU structure.
+     * @param   offApicReg      The APIC register offset which was updated.
      */
     DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnExportState, (PVMCPUCC pVCpu));
 
+    /**
+     * Updates the APIC state after a write to the APIC page by hardware.
+     *
+     * @returns Strict VBox status code.
+     * @param   pVCpu   The cross context virtual CPU structure.
+     *
+     * @note This is a helper for AVIC/APICv when used on AMD or Intel.
+     */
+    DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnUpdateStateAfterWrite, (PVMCPUCC pVCpu, uint16_t offApicReg));
+
+    /**
+     * Sets the End-Of-Interrupt (EOI) register when the vector corresponding
+     * to the EOI is given.
+     *
+     * @returns Strict VBox status code.
+     * @param   pVCpu       The cross context virtual CPU structure.
+     * @param   uVector     The vector for the attempted EOI.
+     */
+    DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiFast, (PVMCPUCC pVCpu, uint8_t uVector));
+
     /** @name Reserved for future (MBZ).
      * @{ */
     DECLR0CALLBACKMEMBER(int, pfnReserved0, (void));
@@ -636,8 +675,6 @@ typedef struct PDMAPICBACKENDR0
     DECLR0CALLBACKMEMBER(int, pfnReserved3, (void));
     DECLR0CALLBACKMEMBER(int, pfnReserved4, (void));
     DECLR0CALLBACKMEMBER(int, pfnReserved5, (void));
-    DECLR0CALLBACKMEMBER(int, pfnReserved6, (void));
-    DECLR0CALLBACKMEMBER(int, pfnReserved7, (void));
     /** @} */
 } PDMAPICBACKENDR0;
 /** Pointer to ring-0 APIC backend. */
@@ -946,6 +983,8 @@ VMM_INT_DECL(int)           PDMApicSetBaseMsr(PVMCPUCC pVCpu, uint64_t u64BaseMs
 VMM_INT_DECL(int)           PDMApicGetInterrupt(PVMCPUCC pVCpu, uint8_t *pu8Vector, uint32_t *puSrcTag);
 VMM_INT_DECL(int)           PDMApicBusDeliver(PVMCC pVM, uint8_t uDest, uint8_t uDestMode, uint8_t uDeliveryMode, uint8_t uVector,
                                               uint8_t uPolarity, uint8_t uTriggerMode, uint8_t uIoApicPin, uint32_t uTagSrc);
+VMM_INT_DECL(VBOXSTRICTRC)  PDMApicUpdateStateAfterWrite(PVMCPUCC pVCpu, uint16_t offApicReg);
+VMM_INT_DECL(VBOXSTRICTRC)  PDMApicSetEoiFast(PVMCPUCC pVCpu, uint8_t uIsrVector);
 #ifdef IN_RING0
 VMM_INT_DECL(int)           PDMR0ApicGetApicPageForCpu(PCVMCPUCC pVCpu, PRTHCPHYS pHCPhys, PRTR0PTR pR0Ptr, PRTR3PTR pR3Ptr);
 #endif

include/iprt/x86.h

@@ -2395,6 +2395,8 @@ typedef const X86MTRRVAR *PCX86MTRRVAR;
 /** SVM - VM_HSAVE_PA - Physical address for saving and restoring
  *                      host state during world switch. */
 #define MSR_K8_VM_HSAVE_PA                  UINT32_C(0xc0010117)
+/** SVM - AVIC doorbell register. */
+#define MSR_AMD_AVIC_DOORBELL               UINT32_C(0xc001011b)
 
 /** Virtualized speculation control for AMD processors.
  *

src/VBox/VMM/VMMAll/PDMAll.cpp

@@ -72,18 +72,23 @@ VMMDECL(int) PDMGetInterrupt(PVMCPUCC pVCpu, uint8_t *pu8Interrupt)
     int rc = VERR_NO_DATA;
     if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
     {
-        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
-
         uint32_t uTagSrc;
         rc = PDMApicGetInterrupt(pVCpu, pu8Interrupt, &uTagSrc);
         if (RT_SUCCESS(rc))
         {
             VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), *pu8Interrupt);
             Log8(("PDMGetInterrupt: irq=%#x tag=%#x (apic)\n", *pu8Interrupt, uTagSrc));
+            VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
             return VINF_SUCCESS;
         }
-        /* else if it's masked by TPR/PPR/whatever, go ahead checking the PIC. Such masked
-           interrupts shouldn't prevent ExtINT from being delivered. */
+
+        /*
+         * If it's masked by TPR/PPR/whatever, go ahead checking the PIC. Such masked
+         * interrupts shouldn't prevent ExtINT from being delivered. If the interrupt is
+         * deferred for delivery by the hardware, do -not- clear the force-flag here.
+         */
+        if (rc != VERR_APIC_INTR_DEFER)
+            VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
     }
 
     PVMCC pVM = pVCpu->CTX_SUFF(pVM);