Feature/pcie

[parhamsoltani]

The PCIe v4 VHDL implementation includes a common package defining link widths and Gen1–Gen4 speeds, TLP and DLLP types, flow control, LTSSM and power states, along with a core package providing transaction-layer interfaces and PHY lane definitions.
It aligns with AXI4/Avalon interface patterns, and resolves issue #33 as part of the High-Speed Serial Interfaces milestone.

[Paebbels]

@parhamsoltani you could also rebase your branch on top of main or release. This reduces noise (forward/backward merges) in the Git history.

Isn't PCIe interfacing defined by the PIPE interface (fabric side) and a group of LVDS' on the PCB side? Or is your proposal specific or independent of a vendor implementation. I though Xilinx offers a PIPE variant in their IP core.

[parhamsoltani]

I’ve rebased onto release so the history should be clean now.

Regarding the interface the packages are vendor‑independent. The lane record (t_PCIe_Physical_Lane) is just a generic differential pair placeholder, and the TX/RX interfaces sit at the TLP level, so they can connect behind any PIPE‑compliant PHY or vendor block (like Xilinx’s AXI‑Stream TLP output).

Only the test‑results publisher step is failing (infra, not code). The actual regression tests under NVC pass.