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Pull requests: SpinalHDL/SpinalHDL
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flatten nested concatnation operator to make RTL more friendly both for human and EDA tools
#1906
opened May 9, 2026 by
facebreeze
Contributor
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2 tasks
Add default for uninitialized register in jtag
#1902
opened Apr 16, 2026 by
jdavidberger
Contributor
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Add Companion trait for Bundles and MultiData types
#1898
opened Apr 7, 2026 by
cyndquill
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2 tasks done
Add support for automated Vivado IP TCL generation and simulation integration
#1859
opened Dec 19, 2025 by
skylayer
Contributor
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3 tasks done
feat(sv interface): sv interface can be set to blackbox. add header comment when oneFilePerComponent
#1829
opened Oct 23, 2025 by
yportne13
Contributor
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2 tasks
Implement readResponseDelay in AxiMemorySim
#1820
opened Oct 1, 2025 by
louiecaulfield
Contributor
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Ability to remap address for BusSlaveFactory
#1354
opened Mar 13, 2024 by
KireinaHoro
Contributor
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Draft
2 tasks
Verilog generated when using synchronous resets is not understood by SymbiYosys - remove "assert() else begin end"-block generation for now
#1315
opened Feb 19, 2024 by
janschiefer
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feat: protocol simulation API; implemented for AHB
#879
opened Oct 3, 2022 by
numero-744
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