WIP: Minor simulation missing#274
Conversation
|
Funnily enough, part of it (at least the PLL one) is included in #272 that is about to be merged the next days. I would wait until this one is done and then check again. The RAM block will probably still be needed as I don't think it is included in #272, but I would have to check (it is quite a big one..) |
|
Actually, after chatting with @awalsemann I actually removed the PLL block. Since my version was also just a black box, we couldn't think of a good reason to keep it. But I'll chat with @padeken, since if he wants it there's obviously a use case! |
|
Hi Ned, |
|
Well, if you need some sort of PLL in a simulation with more than one clock output, maybe we can make a more flexible simulation solution with instantiating clock dividers in the PLL replacement module? |
|
Yes, and writing this I can also provide the not sim module for the RAM, which should be more efificent, but I need to test this first |
|
So you need the RAM simulation module to work on a more advanced PLL one? Then we could split this and merge the RAM first. |
|
I think I will talk to Ned and we will make a better PLL sim and the RAM maybe I will test first and then put it here. |
|
I belive if you need a more advanced model for a PLL, just use an encrypted model from AMD or use one of the exitsing open models available, like this one: https://github.com/nmi-leipzig/sim-x-pll |
Hi I would like to have these sim stand-ins in basil. I think they are useful for more projects.