feat(io-pins): add 16-bit input and output pin blocks#571
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jrp2026 wants to merge 3 commits intoSebLague:mainfrom
Open
feat(io-pins): add 16-bit input and output pin blocks#571jrp2026 wants to merge 3 commits intoSebLague:mainfrom
jrp2026 wants to merge 3 commits intoSebLague:mainfrom
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- Add Bit16 = 16 to PinBitCount enum - Add In_16Bit and Out_16Bit to ChipType enum - Register IN-16 and OUT-16 names in ChipTypeHelper.Names - Update GetPinType() and IsInputOrOutputPin() switch statements for Bit16 - Register CreateInputOrOutputPin() calls in BuiltinChipCreator - Add In_16Bit / Out_16Bit to the IN/OUT chip collection in BuiltinCollectionCreator - Add StateGridDimensions case (8x2) for Bit16 in DevPinInstance - Add PinHeight16Bit constant to DrawSettings (same height as Bit8, 8x2 grid) - Add Bit16 case to PinHeightFromBitCount in SubChipInstance The simulation layer already natively supports 16 data bits via its uint32 state format (upper 16 bits = tristate flags, lower 16 bits = data). Wire rendering and multi-bit dev pin drawing are already data-driven and require no changes.
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Can you make a build please ? I really would try it. |
satredewey
approved these changes
Apr 15, 2026
- Add Split_16To8Bit, Split_16To1Bit, Merge_8To16Bit, Merge_1To16Bit to ChipType enum - Register chip names in ChipTypeHelper (16-8BIT, 16-1BIT, 8-16BIT, 1-16BIT) - Register chip creation calls in BuiltinChipCreator - Add chips to MERGE/SPLIT UI collection in BuiltinCollectionCreator - Implement simulation logic in Simulator.cs: * Split_16To8Bit: splits 16-bit into two 8-bit (high/low bytes) * Split_16To1Bit: splits 16-bit into 16 individual 1-bit outputs * Merge_8To16Bit: merges two 8-bit inputs into one 16-bit output * Merge_1To16Bit: merges 16 individual 1-bit inputs into one 16-bit output
The 16-bit input/output pins have an 8x2 toggle grid (twice as wide as 8-bit's 4x2 grid), so the wire connection point needs to be further out. Changed gridDst from 9 to 13 for Bit16 to position the pin at the proper distance from the handle.
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The simulation layer already natively supports 16 data bits via its uint32 state format (upper 16 bits = tristate flags, lower 16 bits = data). Wire rendering and multi-bit dev pin drawing are already data-driven and require no changes.