Releases: Samal2005/Advanced-Two-Level-Cache-Controller
Releases · Samal2005/Advanced-Two-Level-Cache-Controller
Initial Stable Release
Version 1.0
Features
- Two-Level Cache Architecture
- L1 Direct Mapped Cache
- L2 4-Way Set Associative Cache
- LRU Replacement Policy
- Write Back Policy
- No Write Allocate Policy
- FPGA Implementation Support
- Simulation Verification
Tools Used
- Verilog HDL
- Xilinx Vivado
- FPGA Development Board
Status
Initial stable version of the cache controller implementation.