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board: stm32mp2: fix fwu_mdata node updating #5

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65ae766
ARM: dts: stm32: Sync DT with kernel v6.6-stm32mp-r2-rc6-preint5
Jan 13, 2025
ef3fe8a
board: stm32pm2: support st,eth-clk-sel property
GseoC May 19, 2025
8568c9f
configs: stm32mp23: align with STM32MP25 config
Yann-lms May 28, 2025
e30324e
arm: mach-stm32mp: stm32mp23: add internal RAMs mapping
Yann-lms May 28, 2025
b8efe7e
arm: stm32mp: add Rev.Y and Rev.X support for STM32MP23
Yann-lms May 28, 2025
64beae9
Prepare v2023.10-stm32mp-r2-rc8
Mar 3, 2025
40da460
board: stm32mp2: fix fwu_mdata node updating
passgat Dec 9, 2025
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2 changes: 1 addition & 1 deletion Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
VERSION = 2023
PATCHLEVEL = 10
SUBLEVEL =
EXTRAVERSION = -stm32mp-r1.2
EXTRAVERSION = -stm32mp-r2-rc8
NAME =

# *DOCUMENTATION*
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15 changes: 15 additions & 0 deletions arch/arm/dts/stm32mp13-pinctrl.dtsi
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Expand Up @@ -276,6 +276,21 @@
};
};

pwm1_ch3n_pins_a: pwm1-ch3n-0 {
pins {
pinmux = <STM32_PINMUX('E', 12, AF1)>; /* TIM1_CH3N */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};

pwm1_ch3n_sleep_pins_a: pwm1-ch3n-sleep-0 {
pins {
pinmux = <STM32_PINMUX('E', 12, ANALOG)>; /* TIM1_CH3N */
};
};

pwm3_pins_a: pwm3-0 {
pins {
pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
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39 changes: 37 additions & 2 deletions arch/arm/dts/stm32mp131.dtsi
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Expand Up @@ -161,6 +161,30 @@
interrupt-parent = <&intc>;
ranges;

sram1: sram@30000000 {
compatible = "mmio-sram";
reg = <0x30000000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x30000000 0x4000>;
};

sram2: sram@30004000 {
compatible = "mmio-sram";
reg = <0x30004000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x30004000 0x2000>;
};

sram3: sram@30006000 {
compatible = "mmio-sram";
reg = <0x30006000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x30006000 0x2000>;
};

timers2: timer@40000000 {
#address-cells = <1>;
#size-cells = <0>;
Expand Down Expand Up @@ -1134,6 +1158,7 @@
iwdg2: watchdog@5a002000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5a002000 0x400>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
clock-names = "pclk", "lsi";
status = "disabled";
Expand All @@ -1147,6 +1172,15 @@
status = "disabled";
};

iwdg1: watchdog@5c003000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5c003000 0x400>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc IWDG1>, <&scmi_clk CK_SCMI_LSI>;
clock-names = "pclk", "lsi";
status = "disabled";
};

rtc: rtc@5c004000 {
compatible = "st,stm32mp1-rtc";
reg = <0x5c004000 0x400>;
Expand Down Expand Up @@ -1324,8 +1358,9 @@
#address-cells = <1>;
#size-cells = <0>;
dmas = <&dmamux1 85 0x400 0x01>,
<&dmamux1 86 0x400 0x01>;
dma-names = "rx", "tx";
<&dmamux1 86 0x400 0x01>,
<&mdma 0 0x3 0x1200000a 0 0>;
dma-names = "rx", "tx", "rxm2m";
access-controllers = <&etzpc 19>;
status = "disabled";
};
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45 changes: 35 additions & 10 deletions arch/arm/dts/stm32mp135f-dk.dts
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Expand Up @@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/rtc/rtc-stm32.h>
#include "stm32mp135.dtsi"
#include "stm32mp13xf.dtsi"
Expand Down Expand Up @@ -36,6 +37,7 @@
framebuffer {
compatible = "simple-framebuffer";
clocks = <&rcc LTDC_PX>;
lcd-supply = <&scmi_v3v3_sw>;
status = "disabled";
};
};
Expand Down Expand Up @@ -99,10 +101,11 @@
};

panel_backlight: panel-backlight {
compatible = "gpio-backlight";
gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>;
default-on;
default-brightness-level = <1>;
compatible = "pwm-backlight";
pwms = <&pwm1 2 1000000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
default-brightness-level = <10>;
power-supply = <&scmi_v3v3_sw>;
status = "okay";
};

Expand All @@ -112,6 +115,7 @@
backlight = <&panel_backlight>;
power-supply = <&scmi_v3v3_sw>;
data-mapping = "bgr666";
default-on;
status = "okay";

width-mm = <105>;
Expand Down Expand Up @@ -450,23 +454,23 @@
reg = <VOLTD_SCMI_STPMIC1_BUCK4>;
regulator-name = "vddcore";
};
scmi_vdd_adc: regulator@10 {
scmi_vdd_adc: regulator@a {
reg = <VOLTD_SCMI_STPMIC1_LDO1>;
regulator-name = "vdd_adc";
};
scmi_vdd_usb: regulator@13 {
scmi_vdd_usb: regulator@d {
reg = <VOLTD_SCMI_STPMIC1_LDO4>;
regulator-name = "vdd_usb";
};
scmi_vdd_sd: regulator@14 {
scmi_vdd_sd: regulator@e {
reg = <VOLTD_SCMI_STPMIC1_LDO5>;
regulator-name = "vdd_sd";
};
scmi_v1v8_periph: regulator@15 {
scmi_v1v8_periph: regulator@f {
reg = <VOLTD_SCMI_STPMIC1_LDO6>;
regulator-name = "v1v8_periph";
};
scmi_v3v3_sw: regulator@19 {
scmi_v3v3_sw: regulator@13 {
reg = <VOLTD_SCMI_STPMIC1_PWR_SW2>;
regulator-name = "v3v3_sw";
};
Expand Down Expand Up @@ -511,9 +515,30 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi5_pins_a>;
pinctrl-1 = <&spi5_sleep_pins_a>;
sram = <&spi5_dma_pool>;
status = "disabled";
};

&sram2 {
spi5_dma_pool: dma-sram@1000 {
reg = <0x1000 0x1000>;
pool;
};
};

&timers1 {
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
pwm1: pwm {
pinctrl-0 = <&pwm1_ch3n_pins_a>;
pinctrl-1 = <&pwm1_ch3n_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
};

&timers3 {
/delete-property/dmas;
/delete-property/dma-names;
Expand Down Expand Up @@ -625,7 +650,7 @@
bluetooth {
shutdown-gpios = <&mcp23017 13 GPIO_ACTIVE_HIGH>;
compatible = "brcm,bcm43438-bt";
max-speed = <3000000>;
max-speed = <2000000>;
vbat-supply = <&v3v3_ao>;
vddio-supply = <&v3v3_ao>;
};
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/dts/stm32mp13xa.dtsi
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@@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/dts/stm32mp13xd.dtsi
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@@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/dts/stm32mp15-m4-srm-pinctrl.dtsi
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@@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/dts/stm32mp15-m4-srm.dtsi
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@@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
Expand Down
24 changes: 14 additions & 10 deletions arch/arm/dts/stm32mp151.dtsi
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Expand Up @@ -32,17 +32,10 @@
compatible = "operating-points-v2";
opp-shared;

opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1200000>;
opp-supported-hw = <0x2>;
opp-suspend;
};

opp-650000000 {
opp-hz = /bits/ 64 <650000000>;
opp-microvolt = <1200000>;
opp-supported-hw = <0x1>;
opp-supported-hw = <0x3>;
};

opp-800000000 {
Expand Down Expand Up @@ -596,6 +589,7 @@
iwdg2: watchdog@5a002000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5a002000 0x400>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
clock-names = "pclk", "lsi";
status = "disabled";
Expand Down Expand Up @@ -632,6 +626,15 @@
status = "disabled";
};

iwdg1: watchdog@5c003000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5c003000 0x400>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
clock-names = "pclk", "lsi";
status = "disabled";
};

rtc: rtc@5c004000 {
compatible = "st,stm32mp1-rtc";
reg = <0x5c004000 0x400>;
Expand Down Expand Up @@ -1399,8 +1402,9 @@
clocks = <&rcc SPI4_K>;
resets = <&rcc SPI4_R>;
dmas = <&dmamux1 83 0x400 0x01>,
<&dmamux1 84 0x400 0x01>;
dma-names = "rx", "tx";
<&dmamux1 84 0x400 0x01>,
<&mdma1 0 0x3 0x1200000a 0 0>;
dma-names = "rx", "tx", "rxm2m";
access-controllers = <&etzpc 53>;
status = "disabled";
};
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/dts/stm32mp157a-dk1-scmi.dtsi
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@@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/dts/stm32mp157a-ed1-scmi.dtsi
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@@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/dts/stm32mp157a-ed1.dts
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@@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/dts/stm32mp157a-ev1-scmi.dtsi
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@@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
Expand Down
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