fix(linker): correct cross-toolchain memory map inconsistencies#8
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Found by cross-checking each example's GCC (STM32CubeIDE)/IAR (EWARM)/ Keil (MDK-ARM) linker scripts against each other and against known-good Templates sibling projects, following the same audit already done for STM32CubeG0/G4/H5/H7/L0/L4/L5/U5/WB/WBA/WL/F0/F1/F4/F7 in this repo family. 1. Applications/OpenBootloader (NUCLEO-C031C6, STM32C031C6, 32K flash total): GCC's .ld declared a 27K bootloader region; IAR's .icf (ROM_end 0x08003BFF) and Keil's top-level <IROM>/<Cpu> tags both agree on 15K (0x3C00). Keil's OCR_RVCT4 entry had drifted to 0x8000 (32K, exactly the whole chip - a giveaway that it was never customized from the device-pack default), disagreeing with its own top-level IROM tag in the same file. Fixed GCC's .ld to 15K and Keil's OCR_RVCT4 Size to 0x3c00 to match IAR and Keil's own top-level tag. 2. Applications/FileX/Fx_SRAM_File_Edit_Standalone and Applications/ThreadX/Tx_LowPower and Tx_Thread_Creation (NUCLEO-C092RC, STM32C092RC, 256K flash / 30K RAM): all three projects' GCC .ld and Keil .uvprojx (both the <Cpu> summary line and the IRAM/IROM/OCR_RVCT4 fields) declared only 128K flash / 24K RAM - half of the chip's actual capacity on the flash side and less than the actual RAM. This board's own Templates project confirms the real 256K/30K split. Fixed GCC's .ld MEMORY block and Keil's <Cpu> line + IRAM/IROM/OCR_RVCT4/OCR_RVCT9 entries on all three projects to match. No local ARM toolchain (arm-none-eabi-gcc/IAR/Keil) available to compile/link-test these changes; verification relied on address-arithmetic cross-referencing against multiple independent references per finding (Templates gold standards, IAR's region boundaries, and Keil's own top-level IROM/Cpu tags vs its OCR_RVCT entries within the same file). Signed-off-by: 94xhn <87560781+94xhn@users.noreply.github.com>
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Not tied to a specific existing issue - found by systematically cross-checking each example's GCC (STM32CubeIDE)/IAR (EWARM)/Keil (MDK-ARM) linker scripts against each other and against known-good
Templatessibling projects for the same chip, following the same methodology already used for STM32CubeG0, STM32CubeG4, STM32CubeH5, STM32CubeH7, STM32CubeL0, STM32CubeL4, STM32CubeL5, STM32CubeU5, STM32CubeWB, STM32CubeWBA, STM32CubeWL, STM32CubeF0, STM32CubeF1, STM32CubeF4, and STM32CubeF7 in this repo family.1.
Applications/OpenBootloader(NUCLEO-C031C6, STM32C031C6, 32K flash total) - GCC undershoots, Keil's OCR entry disagrees with its own fileGCC's
.lddeclared a 27K bootloader region. IAR's.icf(ROM_end=0x08003BFF) and Keil's own top-level<IROM>/<Cpu>tags both agree the real bootloader region is 15K (0x3C00). Keil'sOCR_RVCT4entry (the field that actually gets linked) had drifted to0x8000(32K - exactly the whole chip's flash capacity, a giveaway it was never customized away from the device-pack default), disagreeing with its own top-levelIROMtag in the same file. Fixed GCC's.ldto 15K and Keil'sOCR_RVCT4Sizeto0x3c00to match IAR and Keil's own top-level tag.2.
Applications/FileX/Fx_SRAM_File_Edit_Standalone,Applications/ThreadX/Tx_LowPower,Applications/ThreadX/Tx_Thread_Creation(NUCLEO-C092RC, STM32C092RC, 256K flash / 30K RAM) - GCC and Keil both at half capacityAll three projects' GCC
.ldand Keil.uvprojx(both the<Cpu>summary line and theIRAM/IROM/OCR_RVCT4/OCR_RVCT9fields) declared only 128K flash / 24K RAM - half the chip's actual flash capacity and less than its actual RAM. This board's ownTemplatesproject confirms the real 256K/30K split. Fixed GCC's.ldMEMORYblock and Keil's<Cpu>line plusIRAM/IROM/OCR_RVCT4/OCR_RVCT9entries on all three projects to match.Test plan
No local ARM toolchain (arm-none-eabi-gcc/IAR/Keil) available to compile/link-test these, so verification relied on address-arithmetic cross-referencing against multiple independent references per finding:
Templatesgold standards, IAR's region boundaries, and Keil's own top-levelIROM/Cputags cross-checked against itsOCR_RVCTentries within the same file.Disclosure
Generative AI (Claude) was used to help investigate this (systematic cross-toolchain linker script comparison) and implement/verify the fixes. All changes were reviewed by me before submission.