Pinned Loading

1. CPSATr CPSATr Public

   Python

2. Folded-Bias-Decomposition-paper Folded-Bias-Decomposition-paper Public

   Verilog

3. mmig-logic-synthesis-extension mmig-logic-synthesis-extension Public

   AOIG, MIG, and mMIG benchmark suite with Vivado-based FPGA evaluation for the ISVLSI extension study.

   Verilog

4. mMIG-benchmark-flow mMIG-benchmark-flow Public

   Benchmark generation and FPGA flow for mMIG paper artifacts

   Python

5. cancellation-monoid-majority-circuits cancellation-monoid-majority-circuits Public

   Exact and approximate odd-input majority circuit generation and evaluation in Mockturtle

   Verilog

6. mmig-esl-artifact mmig-esl-artifact Public

   Artifact for "minority-Majority Inverter Graphs for Inverter-Aware AQFP-Oriented Logic Optimization" — source code, pre-computed results, and reproduction scripts for Table 1

   C++