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| 1 | +diff --git a/ports/esp32/esp32_common.cmake b/ports/esp32/esp32_common.cmake |
| 2 | +index e3b1b81..6ec1f26 100644 |
| 3 | +--- a/ports/esp32/esp32_common.cmake |
| 4 | ++++ b/ports/esp32/esp32_common.cmake |
| 5 | +@@ -311,6 +311,15 @@ endforeach() |
| 6 | + # Include the main MicroPython cmake rules. |
| 7 | + include(${MICROPY_DIR}/py/mkrules.cmake) |
| 8 | + |
| 9 | ++if(CONFIG_IDF_TARGET_ARCH_RISCV AND MICROPY_FROZEN_CONTENT) |
| 10 | ++ # Frozen native code is emitted as byte arrays in a code section with a |
| 11 | ++ # 4-byte alignment (tools/mpy-tool.py). With linker relaxation on, the |
| 12 | ++ # assembler pads that alignment with R_RISCV_ALIGN NOPs, which cannot |
| 13 | ++ # cover odd sizes ("can't relax section"); the file holds no code that |
| 14 | ++ # could be relaxed, so assemble it without relaxation. |
| 15 | ++ set_source_files_properties(${MICROPY_FROZEN_CONTENT} PROPERTIES COMPILE_OPTIONS "-mno-relax") |
| 16 | ++endif() |
| 17 | ++ |
| 18 | + # Generate source files for named pins (requires mkrules.cmake for MICROPY_GENHDR_DIR). |
| 19 | + |
| 20 | + set(GEN_PINS_PREFIX "${MICROPY_PORT_DIR}/boards/pins_prefix.c") |
| 21 | +diff --git a/tools/mpy-tool.py b/tools/mpy-tool.py |
| 22 | +index 67e2cbf..a61b0cc 100644 |
| 23 | +--- a/tools/mpy-tool.py |
| 24 | ++++ b/tools/mpy-tool.py |
| 25 | +@@ -1254,13 +1254,19 @@ class RawCodeNative(RawCode): |
| 26 | + MP_NATIVE_ARCH_ARMV6, |
| 27 | + MP_NATIVE_ARCH_XTENSA, |
| 28 | + MP_NATIVE_ARCH_XTENSAWIN, |
| 29 | ++ MP_NATIVE_ARCH_RV32IMC, |
| 30 | ++ MP_NATIVE_ARCH_RV64IMC, |
| 31 | + ): |
| 32 | +- # ARMV6 or Xtensa -- four byte align. |
| 33 | ++ # ARMV6, Xtensa or RISC-V -- four byte align. RISC-V needs only two, |
| 34 | ++ # but the assembler never pads a 2-byte alignment inside a code |
| 35 | ++ # section, so arrays after an odd-sized one would start at an odd |
| 36 | ++ # address (a 4-byte one is padded once relaxation is off, see |
| 37 | ++ # ports/esp32/esp32_common.cmake). |
| 38 | + self.fun_data_attributes += " __attribute__ ((aligned (4)))" |
| 39 | + elif ( |
| 40 | + MP_NATIVE_ARCH_ARMV6M <= config.native_arch <= MP_NATIVE_ARCH_ARMV7EMDP |
| 41 | +- ) or MP_NATIVE_ARCH_RV32IMC <= config.native_arch <= MP_NATIVE_ARCH_RV64IMC: |
| 42 | +- # ARMVxxM or RV{32,64}IMC -- two byte align. |
| 43 | ++ ): |
| 44 | ++ # ARMVxxM -- two byte align. |
| 45 | + self.fun_data_attributes += " __attribute__ ((aligned (2)))" |
| 46 | + |
| 47 | + def disassemble(self): |
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