Fix CoreX FP8 dot lowering

[voltjia]

Summary

• add an auto|none|float16 Triton backend option for CoreX E5M2 block-dot lowering
• select the float16 operand fallback from CoreX Triton package metadata while leaving non-CoreX source unchanged
• cover option validation, cache behavior, source generation, unknown SSA dtypes, and repeated dot operands

CoreX Triton 3.1.0+corex.4.4.0 miscompiles direct E5M2 tl.dot, while E5M2 loads, conversions, and scalar FMAs are correct. The fallback upcasts only E5M2 block-dot operands to FP16 before tl.dot; it is limited to source/JIT generation and does not claim FP8 AOT support. Cross-host source generation can opt in explicitly with fp8_dot_fallback="float16".

The three-host full run used integration SHA e5a06f01db6db817d139620be8433da9858dd95b, which contains this commit with an identical stable patch-id plus the separately submitted adaptation fixes.

pytest output:

Backend/compiler/cache/SSA tests: 83 passed
NVIDIA focused fallback tests: 19 passed; FP8/FP16 matmul and addmm: 4 passed
Hygon focused fallback tests: 19 passed; FP8 matmul/addmm and FP16 addmm: 3 passed
Iluvatar CoreX 4.4 focused fallback tests: 19 passed; FP8/FP16 matmul and addmm: 4 passed

Integration SHA e5a06f01:
NVIDIA: 450 passed, 2 skipped in 1917.03s
Hygon: 431 passed, 21 skipped in 2044.69s
Iluvatar CoreX 4.4: 423 passed, 29 skipped in 1377.08s