docs: add TROUBLESHOOTING.md#6
Merged
Merged
Conversation
Add a buffered, crash-safe telemetry logger that records the 100 Hz
control loop to an on-board SD card as a stream of CRC-checked MAVLink v2
frames (".bin" flight log), parseable by standard tooling.
- arm/mavlink_sd_logger.h: header-only MavlinkSdLogger. Canonical
MCRF4XX CRC, MAVLink v2 framing, block-buffered writes, periodic +
shutdown flush. SD-over-SPI sink abstracted behind FatFs-shaped
write/sync callbacks. Per-tick CA_TELEM record; optional stock
NAMED_VALUE_* for ground stations under MAVLINK_AVAILABLE.
- arm/drone_main.cpp: log each control tick, periodic fsync, flush and
close on shutdown with a stats summary.
- arm/test_mavlink_logger.cpp: 11 unit tests (CRC known-answer, framing,
field round-trip, buffering, oversize, write-failure recovery, raw
tee, guards). Wired into arm `make test` and root `make test-arm`/CI.
- mavlink_bridge.h: silence two unused-parameter warnings now that the
header is pulled into the main build.
…latency - Add link-time optimization (-flto) to the ARM release build (RELEASE_FLAGS); -O3 was already enabled. - Add loop_profiler.h: a zero-heap, per-stage latency accumulator (count / mean / max us) and a 'make profile' target (-DPROFILE_LOOP). Production builds compile the probe macros to no-ops, so the flight binary is unaffected. - Instrument the control loop in drone_main.cpp across nine stages (read_flow, predict, track, evade, write_cmd, console_log, bin_log, flush, TOTAL). - Add docs/loop-latency.md documenting methodology, measured worst case (482 us, 4.8% of the 10 ms budget), and the SD fsync real-hardware caveat.
Cover common build/sim/deploy issues: Vitis HLS licensing, CUDA version mismatch, MAVLink port conflicts, ARM cross-compilation, event camera drivers, and SD card logging failures. Grounded in the actual toolchain (arm/Makefile, fpga/build.tcl, config.yaml, mavlink_sd_logger.h). JUNE10DO Person 7 task 4.
- deploy: arm/Makefile hardcodes root@192.168.1.10 with no DEPLOY_HOST override variable; show direct scp instead of an invented make var - cross-toolchain: list both gnueabihf and aarch64 apt package names explicitly to avoid pairing a 64-bit package with a 32-bit error
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Summary
Adds
TROUBLESHOOTING.mdcovering common build/sim/deploy issues, and links it fromCONTRIBUTING.md.Self-contained starter task (JUNE10DO, Person 7, task 4). Docs only — no code changes.
Sections
settings64.sh, and the no-licensemake test-fpgapath viahls_compat.hmodels/inference.py, why training needs a GPU but conversion/inference don'tlsof/dialout, CRC-extra notes.o/LTO/-ffast-mathpitfallsrequirements.txt, recorded-event dev path, ring-buffer evictionf_syncon shutdown,mavlogdumpparsing,loop_profilerkFlushlatencyEach section is grounded in the actual toolchain (
arm/Makefile,fpga/build.tcl,fpga/config.yaml,arm/mavlink_sd_logger.h,arm/mavlink_bridge.h) and points to the hardware-free sim/test paths where they exist.Test plan