This repository provides AXI stream components to compute the square root of a number.
Three variants are available:
-
Combinatorial component: The delays of all iteration stages and the final rounding stage sum up, thus the overall delay is quite high.
-
Pipelined component: Behind each iteration stage and behind the final rounding stage a synchronization element for Valid and Data is placed, thus the delay of each stage is low. In the backpressure direction a synchronization element for the Ready signal is placed in the middle and at the top of the pipeline. The pipeline delay is determined by the number of stages, one stage per digit plus the final rounding stage.
-
Sequential component: This component is composed of a data path and a control path. It iterates for several clock cycles to compute the root from the number. The number of iterations is determined by the number of digits plus one iteration for rounding and outputting the root.
Some more information is provided in these slides.