arm64: dts: aspeed: configure SCU1 uart-clk-source#281
Open
rajaganeshr wants to merge 1 commit into
Open
Conversation
rajaganeshr
requested review from
aasboddu,
ankitaprasad2206,
ashok2ku,
mahkurap and
modolaty
mahkurap
approved these changes
Jul 9, 2026
| #size-cells = <2>; | ||
| #clock-cells = <1>; | ||
| #reset-cells = <1>; | ||
| uart-clk-source = <0xff0>; /* bit[x]: 0 uxclk, 1 huxclk */ |
Collaborator
There was a problem hiding this comment.
@rajaganeshr a question: as per this bit mask UART0 - UART3 are still sourced with clock from UXCLK, and UART 4 - to UART are sourced with clock from HUXCLK for higher baud rates. Which UART did you use to verify the HUXCLK, and which baudrate did you use?. this is for my understanding. thank you.
Collaborator
Author
There was a problem hiding this comment.
To use high baud rate ( > 115200bps), we must use HUXCLK as clock source.
Tested ttyS13 ( P0 UART) upto 948k (~1M). Baud rate above that require LTPI freq greater than 100Mhz.
realized now that ttyS3 also needs HUXCLK (P1 UART), will refresh this submission to use HUXCLK for all UARTs.
Add uart-clk-source to the AST2700 SCU1 syscon node. UART defaults to UXCLK (supports up to 115200 baud). For high-speed UART (>115200), UART clock source must switch to HUXCLK. The uart-clk-source bitfield controls this per UARTx (LSB-first), so set it to <0xfff> for all instances. Tested: Verified on kenya. uart-clk-source is present under syscon1:syscon@14c02000 with value <0xff0>. Signed-off-by: Rajaganesh Rathinasabapathi <Rajaganesh.Rathinasabapathi@amd.com>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Add uart-clk-source to the AST2700 SCU1 syscon node.
UART defaults to UXCLK (supports up to 115200 baud). For high-speed UART (>115200), UART clock source must switch to HUXCLK.
The uart-clk-source bitfield controls this per UARTx (LSB-first), so set it to <0xff0> for the required high-speed UART instances.
Tested: Verified on kenya. uart-clk-source is present under syscon1:syscon@14c02000 with value <0xff0>.