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Added support for Digilent Genesys 2 target
- ported S7 RGMII from LiteEth - added support for 1x non-IO SPI flash (had problems with x4 IO operation) - added Digilent Genesys 2 target
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‎misoc/cores/liteeth_mini/phy/s7rgmii.py

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Original file line numberDiff line numberDiff line change
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#
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# This file is part of LiteEth, backported to MiSoC.
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#
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# Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2022-2022 Mikolaj Sowinski <msowinski@technosystem.com.pl>
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# SPDX-License-Identifier: BSD-2-Clause
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# RGMII PHY for 7-Series Xilinx FPGA
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from misoc.cores.liteeth_mini.common import *
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class LiteEthPHYHWReset(Module):
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def __init__(self, cycles=256):
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self.reset = Signal()
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# # #
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counter = Signal(max=cycles + 1)
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counter_done = Signal()
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counter_ce = Signal()
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self.sync += If(counter_ce, counter.eq(counter + 1))
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self.comb += [
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counter_done.eq(counter == cycles),
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counter_ce.eq(~counter_done),
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self.reset.eq(~counter_done)
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]
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class LiteEthPHYRGMIITX(Module):
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def __init__(self, pads):
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self.sink = sink = stream.Endpoint(eth_phy_layout(8))
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# # #
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tx_ctl_obuf = Signal()
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tx_data_obuf = Signal(4)
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self.specials += [
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Instance("ODDR",
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p_DDR_CLK_EDGE = "SAME_EDGE",
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i_C = ClockSignal("eth_tx"),
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i_CE = 1,
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i_S = 0,
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i_R = 0,
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i_D1 = sink.stb,
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i_D2 = sink.stb,
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o_Q = tx_ctl_obuf,
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),
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Instance("OBUF",
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i_I = tx_ctl_obuf,
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o_O = pads.tx_ctl,
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),
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]
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for i in range(4):
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self.specials += [
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Instance("ODDR",
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p_DDR_CLK_EDGE = "SAME_EDGE",
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i_C = ClockSignal("eth_tx"),
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i_CE = 1,
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i_S = 0,
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i_R = 0,
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i_D1 = sink.data[i],
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i_D2 = sink.data[4+i],
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o_Q = tx_data_obuf[i],
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),
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Instance("OBUF",
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i_I = tx_data_obuf[i],
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o_O = pads.tx_data[i],
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)
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]
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self.comb += sink.ack.eq(1)
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class LiteEthPHYRGMIIRX(Module):
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def __init__(self, pads, rx_delay=2e-9, iodelay_clk_freq=200e6):
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self.source = source = stream.Endpoint(eth_phy_layout(8))
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# # #
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assert iodelay_clk_freq in [200e6, 300e6, 400e6]
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iodelay_tap_average = 1 / (2*32 * iodelay_clk_freq)
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rx_delay_taps = round(rx_delay / iodelay_tap_average)
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assert rx_delay_taps < 32, "Exceeded ODELAYE2 max value: {} >= 32".format(rx_delay_taps)
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rx_ctl_ibuf = Signal()
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rx_ctl_idelay = Signal()
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rx_ctl = Signal()
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rx_data_ibuf = Signal(4)
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rx_data_idelay = Signal(4)
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rx_data = Signal(8)
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self.specials += [
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Instance("IBUF", i_I=pads.rx_ctl, o_O=rx_ctl_ibuf),
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Instance("IDELAYE2",
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p_IDELAY_TYPE = "FIXED",
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p_IDELAY_VALUE = rx_delay_taps,
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p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
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i_C = 0,
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i_LD = 0,
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i_CE = 0,
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i_LDPIPEEN = 0,
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i_INC = 0,
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i_IDATAIN = rx_ctl_ibuf,
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o_DATAOUT = rx_ctl_idelay,
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),
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Instance("IDDR",
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p_DDR_CLK_EDGE = "SAME_EDGE_PIPELINED",
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i_C = ClockSignal("eth_rx"),
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i_CE = 1,
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i_S = 0,
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i_R = 0,
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i_D = rx_ctl_idelay,
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o_Q1 = rx_ctl,
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o_Q2 = Signal(),
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)
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]
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for i in range(4):
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self.specials += [
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Instance("IBUF",
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i_I = pads.rx_data[i],
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o_O = rx_data_ibuf[i],
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),
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Instance("IDELAYE2",
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p_IDELAY_TYPE = "FIXED",
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p_IDELAY_VALUE = rx_delay_taps,
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p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
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i_C = 0,
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i_LD = 0,
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i_CE = 0,
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i_LDPIPEEN = 0,
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i_INC = 0,
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i_IDATAIN = rx_data_ibuf[i],
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o_DATAOUT = rx_data_idelay[i],
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),
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Instance("IDDR",
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p_DDR_CLK_EDGE = "SAME_EDGE_PIPELINED",
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i_C = ClockSignal("eth_rx"),
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i_CE = 1,
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i_S = 0,
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i_R = 0,
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i_D = rx_data_idelay[i],
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o_Q1 = rx_data[i],
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o_Q2 = rx_data[i+4],
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)
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]
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rx_ctl_d = Signal()
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self.sync += rx_ctl_d.eq(rx_ctl)
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last = Signal()
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self.comb += last.eq(~rx_ctl & rx_ctl_d)
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self.sync += [
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source.stb.eq(rx_ctl),
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source.data.eq(rx_data)
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]
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self.comb += source.eop.eq(last)
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class LiteEthPHYRGMIICRG(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset, tx_delay=2e-9, hw_reset_cycles=256):
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self._reset = CSRStorage()
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# # #
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# RX clock
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self.clock_domains.cd_eth_rx = ClockDomain()
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eth_rx_clk_ibuf = Signal()
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self.specials += [
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Instance("IBUF",
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i_I = clock_pads.rx,
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o_O = eth_rx_clk_ibuf,
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),
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Instance("BUFG",
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i_I = eth_rx_clk_ibuf,
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o_O = self.cd_eth_rx.clk,
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),
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]
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# TX clock
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.clock_domains.cd_eth_tx_delayed = ClockDomain(reset_less=True)
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tx_phase = 125e6*tx_delay*360
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assert tx_phase < 360
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pll_fb = Signal()
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eth_tx_clk = Signal()
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eth_tx_delayed_clk = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=Signal(),
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# VCO @ 1GHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=ClockSignal("eth_rx"), i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 125MHz
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p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=eth_tx_clk,
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# 500MHz
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p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=tx_phase, o_CLKOUT1=eth_tx_delayed_clk,
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p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
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p_CLKOUT3_DIVIDE=5, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
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p_CLKOUT4_DIVIDE=5, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
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),
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Instance("BUFG", i_I=eth_tx_clk, o_O=self.cd_eth_tx.clk),
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Instance("BUFG", i_I=eth_tx_delayed_clk, o_O=self.cd_eth_tx_delayed.clk),
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]
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eth_tx_clk_obuf = Signal()
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self.specials += [
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Instance("ODDR",
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p_DDR_CLK_EDGE = "SAME_EDGE",
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i_C = ClockSignal("eth_tx_delayed"),
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i_CE = 1,
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i_S = 0,
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i_R = 0,
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i_D1 = 1,
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i_D2 = 0,
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o_Q = eth_tx_clk_obuf,
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),
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Instance("OBUF",
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i_I = eth_tx_clk_obuf,
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o_O = clock_pads.tx,
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)
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]
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# Reset
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self.reset = reset = Signal()
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if with_hw_init_reset:
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self.submodules.hw_reset = LiteEthPHYHWReset(cycles=hw_reset_cycles)
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self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
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else:
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self.comb += reset.eq(self._reset.storage)
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if hasattr(pads, "rst_n"):
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self.comb += pads.rst_n.eq(~reset)
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self.specials += [
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AsyncResetSynchronizer(self.cd_eth_tx, reset),
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AsyncResetSynchronizer(self.cd_eth_rx, reset),
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]
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class LiteEthPHYRGMII(Module, AutoCSR):
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dw = 8
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tx_clk_freq = 125e6
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rx_clk_freq = 125e6
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def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9,
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iodelay_clk_freq=200e6, hw_reset_cycles=256):
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self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay, hw_reset_cycles)
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self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
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self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay, iodelay_clk_freq))
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self.sink, self.source = self.tx.sink, self.rx.source

‎misoc/cores/spi_flash.py

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,10 @@ def __init__(self, pads, dummy=15, div=2, with_bitbang=True, endianness="big", d
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"""
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adr_width = 32-log2_int(dw//8)
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self.bus = bus = wishbone.Interface(data_width=dw, adr_width=adr_width)
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spi_width = len(pads.dq)
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if hasattr(pads, "dq"):
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spi_width = len(pads.dq)
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else:
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spi_width = 1
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if with_bitbang:
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self.bitbang = CSRStorage(4)
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self.miso = CSRStatus()
@@ -62,8 +65,16 @@ def __init__(self, pads, dummy=15, div=2, with_bitbang=True, endianness="big", d
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pads.cs_n.reset = 1
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65-
dq = TSTriple(spi_width)
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self.specials.dq = dq.get_tristate(pads.dq)
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if spi_width > 1:
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dq = TSTriple(spi_width)
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self.specials.dq = dq.get_tristate(pads.dq)
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else:
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class TripleMock:
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def __init__(self):
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self.i = pads.miso
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self.o = pads.mosi
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self.oe = Signal()
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dq = TripleMock()
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sr = Signal(max(cmd_width, addr_width, dw))
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if endianness == "big":
@@ -88,7 +99,8 @@ def __init__(self, pads, dummy=15, div=2, with_bitbang=True, endianness="big", d
8899
dq.oe.eq(1)
89100
),
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If(self.bitbang.storage[1],
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self.miso.status.eq(dq.i[1])
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self.miso.status.eq(dq.i) if spi_width == 1 \
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else self.miso.status.eq(dq.i[1])
92104
)
93105
]
94106
if spi_width > 1:

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