On arm64 are float32x2_t is not supported

[mlomonaco]

On an apple silicon + clang this doesnt compile (latest git clone on master):

 typedef xsimd::batch<float, xsimd::make_sized_batch<float, 2>> t_Vector2;
 t_Vector2 a = 2.0f;

Error is:

/opt/compiler-explorer/libs/xsimd/trunk/include/xsimd/types/xsimd_batch.hpp:532:58: error: no matching function for call to 'broadcast<xsimd::make_sized_batch<float, 2> >(float&, xsimd::make_sized_batch<float, 2>)'
  532 |         : types::simd_register<T, A>(kernel::broadcast<A>(val, A {}))
      |                                      ~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~
  • there are 11 candidates
...omissis...

A quick search in xsimd_neon.hpp in the library doesnt show any intrinsic float32x2_t vdup_n_f32(float32_t value) function
I believe assignment operator = also fails for the 2 lanes simd.

Am I missing something?

Thanks

M.

[JohanMabille]

Actually make_sized_batch<T, N> already returns a batch type if possible (meaning if this size is supported on the given architecture). For NEON, we support batches of 4 float scalars only (i.e. wrapping float32x4_t).

[mlomonaco]

Thanks, any plan to add those in the future? I might be able to help

[JohanMabille]

The "difficulty" is that the current design of xsimd is not well adapted for that: an architecture supports a given length of batch per scalar type. A solution could be to add a "fake" architecture, like HALF_NEON (or maybe we could find a better name), or take that need when refactoring the way we handle architecture and introduce "decorators" for specifying additional instruction sets to a particular architecture. My preference would be the fake architecture since it's already possible to implement it, but maybe @serge-sans-paille has a better idea.

[serge-sans-paille]

What about half_batch<type, arch>? It makes sense for Neon, sse/avx/avx512... We need to think a bit about the consequences in terms of class hierachy etc, but it may make sense.

[DiamonDinoia]

What about half_batch<type, arch>?
It makes sense for Neon, sse/avx/avx512...
We need to think a bit about the consequences in terms of class hierachy etc,
but it may make sense.

That would also be interesting in the context of #1130

[mlomonaco]

From my newbie POV, this is what surprised me about the unsupported float32x2_t on ARM.
When I compile this on x86-64 clang -march=skylake-avx512 they all work:

xsimd::make_sized_batch<float, 4>::type u4;
xsimd::make_sized_batch<float, 8>::type u8;
xsimd::make_sized_batch<float, 16>::type u16;

so why not

xsimd::make_sized_batch<float, 2>::type u2;

?