From 13109a73236bb1bd83837f044992d0eedcd93751 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Jul 2026 14:41:10 +0200 Subject: [PATCH 1/7] chore(wl3): update patch Signed-off-by: Frederic Pillon --- .../0001-fix-wl3-HAL-and-LL-warnings.patch | 182 ++++++++---------- 1 file changed, 84 insertions(+), 98 deletions(-) diff --git a/CI/update/patch/HAL/WL3/0001-fix-wl3-HAL-and-LL-warnings.patch b/CI/update/patch/HAL/WL3/0001-fix-wl3-HAL-and-LL-warnings.patch index 6df419dbe5..a9622a679f 100644 --- a/CI/update/patch/HAL/WL3/0001-fix-wl3-HAL-and-LL-warnings.patch +++ b/CI/update/patch/HAL/WL3/0001-fix-wl3-HAL-and-LL-warnings.patch @@ -6,8 +6,7 @@ Subject: [PATCH 1/1] fix(wl3): HAL and LL warnings Signed-off-by: Frederic Pillon --- .../Inc/stm32wl3x_ll_dma.h | 104 ++++++++++++++++++ - .../Src/stm32wl3x_hal_flash_ex.c | 2 +- - 2 files changed, 105 insertions(+), 1 deletion(-) + 1 files changed, 104 insertions(+), 0 deletion(-) diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h index b94790b32..e49d7c53f 100644 @@ -20,7 +19,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } - + @@ -453,6 +454,7 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) @@ -28,7 +27,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } - + @@ -473,6 +475,7 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) @@ -188,7 +187,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } - + @@ -988,6 +1010,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) @@ -196,7 +195,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress); } - + @@ -1009,6 +1032,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) @@ -204,7 +203,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } - + @@ -1030,6 +1054,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) @@ -212,7 +211,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } - + @@ -1053,6 +1078,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) @@ -220,7 +219,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress); } - + @@ -1076,6 +1102,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) @@ -228,7 +227,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } - + @@ -1097,6 +1124,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) @@ -236,7 +235,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } - + @@ -1118,6 +1146,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) @@ -244,7 +243,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } - + @@ -1140,6 +1169,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) @@ -252,7 +251,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID, Request); } - + @@ -1161,6 +1191,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) @@ -260,7 +259,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID)); } - + @@ -1180,6 +1211,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) @@ -268,7 +267,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); } - + @@ -1191,6 +1223,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) @@ -276,7 +275,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); } - + @@ -1202,6 +1235,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) @@ -284,7 +283,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); } - + @@ -1213,6 +1247,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) @@ -292,7 +291,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); } - + @@ -1224,6 +1259,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) @@ -300,7 +299,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); } - + @@ -1235,6 +1271,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) @@ -308,7 +307,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); } - + @@ -1246,6 +1283,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) @@ -316,7 +315,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); } - + @@ -1257,6 +1295,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx) @@ -324,7 +323,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF8) == (DMA_ISR_GIF8)) ? 1UL : 0UL); } - + @@ -1268,6 +1307,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) @@ -332,7 +331,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); } - + @@ -1279,6 +1319,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) @@ -340,7 +339,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); } - + @@ -1290,6 +1331,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) @@ -348,7 +347,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); } - + @@ -1301,6 +1343,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) @@ -356,7 +355,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); } - + @@ -1312,6 +1355,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) @@ -364,7 +363,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); } - + @@ -1323,6 +1367,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) @@ -372,7 +371,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); } - + @@ -1334,6 +1379,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) @@ -380,7 +379,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); } - + @@ -1345,6 +1391,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx) @@ -388,7 +387,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF8) == (DMA_ISR_TCIF8)) ? 1UL : 0UL); } - + @@ -1356,6 +1403,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) @@ -396,7 +395,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); } - + @@ -1367,6 +1415,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) @@ -404,7 +403,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); } - + @@ -1378,6 +1427,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) @@ -412,7 +411,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); } - + @@ -1389,6 +1439,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) @@ -420,7 +419,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); } - + @@ -1400,6 +1451,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) @@ -428,7 +427,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); } - + @@ -1411,6 +1463,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) @@ -436,7 +435,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); } - + @@ -1422,6 +1475,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) @@ -444,7 +443,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); } - + @@ -1433,6 +1487,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx) @@ -452,7 +451,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF8) == (DMA_ISR_HTIF8)) ? 1UL : 0UL); } - + @@ -1444,6 +1499,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) @@ -460,7 +459,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); } - + @@ -1455,6 +1511,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) @@ -468,7 +467,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); } - + @@ -1466,6 +1523,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) @@ -476,7 +475,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); } - + @@ -1477,6 +1535,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) @@ -484,7 +483,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); } - + @@ -1488,6 +1547,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) @@ -492,7 +491,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); } - + @@ -1499,6 +1559,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) @@ -500,7 +499,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); } - + @@ -1510,6 +1571,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) @@ -508,7 +507,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); } - + @@ -1521,6 +1583,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) @@ -516,7 +515,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF8) == (DMA_ISR_TEIF8)) ? 1UL : 0UL); } - + @@ -1532,6 +1595,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) @@ -524,7 +523,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); } - + @@ -1543,6 +1607,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) @@ -532,7 +531,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); } - + @@ -1554,6 +1619,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) @@ -540,7 +539,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); } - + @@ -1565,6 +1631,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) @@ -548,7 +547,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); } - + @@ -1576,6 +1643,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) @@ -556,7 +555,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); } - + @@ -1587,6 +1655,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) @@ -564,7 +563,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); } - + @@ -1598,6 +1667,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) @@ -572,7 +571,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); } - + @@ -1609,6 +1679,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx) @@ -580,7 +579,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF8); } - + @@ -1620,6 +1691,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) @@ -588,7 +587,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); } - + @@ -1631,6 +1703,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) @@ -596,7 +595,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); } - + @@ -1642,6 +1715,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) @@ -604,7 +603,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); } - + @@ -1653,6 +1727,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) @@ -612,7 +611,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); } - + @@ -1664,6 +1739,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) @@ -620,7 +619,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); } - + @@ -1675,6 +1751,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) @@ -628,7 +627,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); } - + @@ -1686,6 +1763,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) @@ -636,7 +635,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); } - + @@ -1697,6 +1775,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx) @@ -644,7 +643,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF8); } - + @@ -1708,6 +1787,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) @@ -652,7 +651,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); } - + @@ -1719,6 +1799,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) @@ -660,7 +659,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); } - + @@ -1730,6 +1811,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) @@ -668,7 +667,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); } - + @@ -1741,6 +1823,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) @@ -676,7 +675,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); } - + @@ -1752,6 +1835,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) @@ -684,7 +683,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); } - + @@ -1763,6 +1847,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) @@ -692,7 +691,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); } - + @@ -1774,6 +1859,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) @@ -700,7 +699,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); } - + @@ -1785,6 +1871,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx) @@ -708,7 +707,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF8); } - + @@ -1796,6 +1883,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) @@ -716,7 +715,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); } - + @@ -1807,6 +1895,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) @@ -724,7 +723,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); } - + @@ -1818,6 +1907,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) @@ -732,7 +731,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); } - + @@ -1829,6 +1919,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) @@ -740,7 +739,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); } - + @@ -1840,6 +1931,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) @@ -748,7 +747,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); } - + @@ -1851,6 +1943,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) @@ -756,7 +755,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); } - + @@ -1862,6 +1955,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) @@ -764,7 +763,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); } - + @@ -1873,6 +1967,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) @@ -772,7 +771,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF8); } - + @@ -1900,6 +1995,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) @@ -780,7 +779,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } - + @@ -1920,6 +2016,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) @@ -788,7 +787,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } - + @@ -1940,6 +2037,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) @@ -796,7 +795,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } - + @@ -1960,6 +2058,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) @@ -804,7 +803,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } - + @@ -1980,6 +2079,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) @@ -812,7 +811,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } - + @@ -2000,6 +2100,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) @@ -820,7 +819,7 @@ index b94790b32..e49d7c53f 100644 + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } - + @@ -2020,6 +2121,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) @@ -845,19 +844,6 @@ index b94790b32..e49d7c53f 100644 return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); } -diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c -index 9cd95caf3..d1b9f3dd0 100644 ---- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c -+++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c -@@ -107,7 +107,7 @@ static void FLASH_Program_OTPWord(uint32_t Address, uint32_t Data); - */ - HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) - { -- HAL_StatusTypeDef status; -+ HAL_StatusTypeDef status = HAL_ERROR; - uint32_t index; - - /* Check the parameters */ --- +-- 2.34.1 From 9b8d4cbe052e3ae404d8bd9107b6658a1a687195 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Jul 2026 14:41:14 +0200 Subject: [PATCH 2/7] system(wl3) update STM32WL3x HAL Drivers to v1.5.0 Included in STM32CubeWL3 FW v1.5.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 17 +- .../STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal.h | 4 +- .../Inc/stm32wl3x_hal_gpio.h | 80 +++--- .../Inc/stm32wl3x_hal_gpio_ex.h | 2 +- .../Inc/stm32wl3x_hal_i2c_ex.h | 38 +-- .../Inc/stm32wl3x_hal_i2s.h | 6 +- .../Inc/stm32wl3x_hal_mrsubg.h | 194 +++++++++++++- .../Inc/stm32wl3x_hal_mrsubg_timer.h | 4 +- .../Inc/stm32wl3x_hal_rcc_ex.h | 12 +- .../Inc/stm32wl3x_hal_smbus_ex.h | 40 +-- .../Inc/stm32wl3x_hal_spi.h | 46 ++-- .../Inc/stm32wl3x_hal_uart.h | 2 +- .../Inc/stm32wl3x_ll_dma.h | 104 -------- .../Inc/stm32wl3x_ll_gpio.h | 2 +- .../Inc/stm32wl3x_ll_mrsubg.h | 237 ++++++++++++++-- .../Inc/stm32wl3x_ll_pwr.h | 181 ++++++++++--- .../Inc/stm32wl3x_ll_rcc.h | 32 +++ .../Inc/stm32wl3x_ll_spi.h | 169 ++++++------ .../Drivers/STM32WL3x_HAL_Driver/LICENSE.md | 2 +- system/Drivers/STM32WL3x_HAL_Driver/README.md | 4 +- .../STM32WL3x_HAL_Driver/Release_Notes.html | 224 +++++++++++++--- .../STM32WL3x_HAL_Driver/SW_Security_Level.md | 47 ++++ .../Src/stm32wl3x_hal_adc.c | 2 +- .../Src/stm32wl3x_hal_flash.c | 4 +- .../Src/stm32wl3x_hal_flash_ex.c | 4 +- .../Src/stm32wl3x_hal_gpio.c | 58 ++-- .../Src/stm32wl3x_hal_i2s.c | 6 +- .../Src/stm32wl3x_hal_mrsubg.c | 252 +++++++++++++----- .../Src/stm32wl3x_hal_mrsubg_timer.c | 2 +- .../Src/stm32wl3x_hal_rcc_ex.c | 18 +- .../Src/stm32wl3x_hal_smartcard.c | 16 +- .../Src/stm32wl3x_hal_spi.c | 223 +++++++++------- .../Src/stm32wl3x_hal_timebase_tim_template.c | 7 + .../Src/stm32wl3x_hal_uart.c | 8 +- .../Src/stm32wl3x_ll_gpio.c | 8 +- .../Src/stm32wl3x_ll_spi.c | 13 +- .../Src/stm32wl3x_ll_utils.c | 5 - .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 38 files changed, 1448 insertions(+), 627 deletions(-) create mode 100644 system/Drivers/STM32WL3x_HAL_Driver/SW_Security_Level.md diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 836d610016..35650fcc17 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -363,7 +363,6 @@ extern "C" { #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI #elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) #define DMA_REQUEST_PSSI DMA_REQUEST_DCMI_PSSI -#define LL_DMAMUX_REQ_PSSI LL_DMAMUX_REQ_DCMI_PSSI #endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4 */ @@ -1918,7 +1917,11 @@ extern "C" { #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM - +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +#define PWR_PVM_USB PWR_PVM_ENABLE +#define PWR_FLAG_PVMOUSB PWR_FLAG_PVMOVDDIO2 +#define PWR_FLAG_PVMO_USB PWR_FLAG_PVMO_VDDIO2 +#endif /* STM32G0C1xx || STM32G0B1xx */ #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING @@ -2031,6 +2034,9 @@ extern "C" { #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK #endif +#if defined (STM32H7RS) +#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO PWR_SMPS_1V8_SUPPLIES_EXT_VDD_SUPPLIES_LDO +#endif /** * @} @@ -2159,6 +2165,13 @@ extern "C" { #define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig #endif /* STM32H7RS || STM32N6 */ +#if defined(STM32N6) +/* alias CMSIS */ +#define CSI_PCR_PWRDOWN_Pos CSI_PCR_NPWRDOWN_Pos +#define CSI_PCR_PWRDOWN_Msk CSI_PCR_NPWRDOWN_Msk +#define CSI_PCR_PWRDOWN CSI_PCR_NPWRDOWN +#endif /* STM32N6 */ + /** * @} */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal.h index a99bef4ecc..9f37dc3155 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal.h @@ -48,8 +48,8 @@ extern "C" { * @brief HAL Driver version number */ #define __STM32WL3X_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WL3X_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ -#define __STM32WL3X_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ +#define __STM32WL3X_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ +#define __STM32WL3X_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WL3X_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WL3X_HAL_VERSION ((__STM32WL3X_HAL_VERSION_MAIN << 24U)\ |(__STM32WL3X_HAL_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_gpio.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_gpio.h index 3b83616aa2..f5899b7603 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_gpio.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_gpio.h @@ -139,10 +139,10 @@ typedef enum * @brief GPIO Output Maximum frequency * @{ */ -#define GPIO_SPEED_FREQ_LOW 0x00000000u /*!< Low speed */ -#define GPIO_SPEED_FREQ_MEDIUM 0x00000001u /*!< Medium speed */ -#define GPIO_SPEED_FREQ_HIGH 0x00000002u /*!< High speed */ -#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u /*!< Very high speed */ +#define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< High speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< Very high speed */ /** * @} */ @@ -151,9 +151,9 @@ typedef enum * @brief GPIO Pull-Up or Pull-Down Activation * @{ */ -#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */ -#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */ +#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */ +#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */ /** * @} */ @@ -215,36 +215,36 @@ typedef enum /** @defgroup GPIO_Private_Constants GPIO Private Constants * @{ */ -#define GPIO_MODE_Pos 0u -#define GPIO_MODE (0x3uL << GPIO_MODE_Pos) -#define MODE_INPUT (0x0uL << GPIO_MODE_Pos) -#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos) -#define MODE_AF (0x2uL << GPIO_MODE_Pos) -#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos) -#define OUTPUT_TYPE_Pos 4u -#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos) -#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos) -#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos) -#define EXTI_MODE_Pos 16u -#define EXTI_MODE (0x3uL << EXTI_MODE_Pos) -#define EXTI_IT (0x1uL << EXTI_MODE_Pos) -#define EXTI_EVT (0x2uL << EXTI_MODE_Pos) -#define DETECTION_TYPE_Pos 18u -#define DETECTION_TYPE (0x1uL << DETECTION_TYPE_Pos) -#define DETECTION_TYPE_EDGE (0x0uL << DETECTION_TYPE_Pos) -#define DETECTION_TYPE_LEVEL (0x1uL << DETECTION_TYPE_Pos) -#define EDGE_SELECTION_Pos 20u -#define EDGE_SELECTION (0x1uL << EDGE_SELECTION_Pos) -#define EDGE_SELECTION_SINGLE (0x0uL << EDGE_SELECTION_Pos) -#define EDGE_SELECTION_BOTH (0x1uL << EDGE_SELECTION_Pos) -#define TRIGGER_MODE_Pos 22u -#define TRIGGER_MODE (0x1uL << TRIGGER_MODE_Pos) -#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos) -#define TRIGGER_FALLING (0x0uL << TRIGGER_MODE_Pos) -#define EDGE_LEVEL_Pos 24u -#define EDGE_LEVEL (0x1uL << EDGE_LEVEL_Pos) -#define EDGE_LOW (0x0uL << EDGE_LEVEL_Pos) -#define EDGE_HIGH (0x1uL << EDGE_LEVEL_Pos) +#define GPIO_MODE_Pos 0U +#define GPIO_MODE (0x3UL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0UL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) +#define MODE_AF (0x2UL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4U +#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16U +#define EXTI_MODE (0x3UL << EXTI_MODE_Pos) +#define EXTI_IT (0x1UL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2UL << EXTI_MODE_Pos) +#define DETECTION_TYPE_Pos 18U +#define DETECTION_TYPE (0x1UL << DETECTION_TYPE_Pos) +#define DETECTION_TYPE_EDGE (0x0UL << DETECTION_TYPE_Pos) +#define DETECTION_TYPE_LEVEL (0x1UL << DETECTION_TYPE_Pos) +#define EDGE_SELECTION_Pos 20U +#define EDGE_SELECTION (0x1UL << EDGE_SELECTION_Pos) +#define EDGE_SELECTION_SINGLE (0x0UL << EDGE_SELECTION_Pos) +#define EDGE_SELECTION_BOTH (0x1UL << EDGE_SELECTION_Pos) +#define TRIGGER_MODE_Pos 22U +#define TRIGGER_MODE (0x1UL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x0UL << TRIGGER_MODE_Pos) +#define EDGE_LEVEL_Pos 24U +#define EDGE_LEVEL (0x1UL << EDGE_LEVEL_Pos) +#define EDGE_LOW (0x0UL << EDGE_LEVEL_Pos) +#define EDGE_HIGH (0x1UL << EDGE_LEVEL_Pos) /** * @} */ @@ -254,11 +254,11 @@ typedef enum */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\ - (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u)) +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) #define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \ - (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) + (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00U) #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_gpio_ex.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_gpio_ex.h index 2584b85655..48bdd056d5 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_gpio_ex.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_gpio_ex.h @@ -139,7 +139,7 @@ extern "C" { * @{ */ -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL : 1uL) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL : 1UL) /** * @} diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2c_ex.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2c_ex.h index f3395066a0..03f2d9c24c 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2c_ex.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2c_ex.h @@ -130,23 +130,31 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) -#if defined(I2C1) +#if defined(I2C1) && defined(I2C2) #define IS_I2C_FASTMODEPLUS(__CONFIG__) ( \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PA0)) == I2C_FASTMODEPLUS_PA0) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PA1)) == I2C_FASTMODEPLUS_PA1) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB10)) == I2C_FASTMODEPLUS_PB10) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB11)) == I2C_FASTMODEPLUS_PB11) ) -#endif /* I2C1 */ - -#if defined(I2C2) + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PA0) == I2C_FASTMODEPLUS_PA0) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PA1) == I2C_FASTMODEPLUS_PA1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB10) == I2C_FASTMODEPLUS_PB10) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB11) == I2C_FASTMODEPLUS_PB11) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PA6) == I2C_FASTMODEPLUS_PA6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PA7) == I2C_FASTMODEPLUS_PA7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PA13) == I2C_FASTMODEPLUS_PA13) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PA14) == I2C_FASTMODEPLUS_PA14) ) +#elif defined(I2C1) #define IS_I2C_FASTMODEPLUS(__CONFIG__) ( \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PA6)) == I2C_FASTMODEPLUS_PA6) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PA7)) == I2C_FASTMODEPLUS_PA7) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PA13)) == I2C_FASTMODEPLUS_PA13) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PA14)) == I2C_FASTMODEPLUS_PA14) ) -#endif /* I2C2 */ - + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PA0) == I2C_FASTMODEPLUS_PA0) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PA1) == I2C_FASTMODEPLUS_PA1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB10) == I2C_FASTMODEPLUS_PB10) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB11) == I2C_FASTMODEPLUS_PB11) ) +#elif defined(I2C2) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ( \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PA6) == I2C_FASTMODEPLUS_PA6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PA7) == I2C_FASTMODEPLUS_PA7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PA13) == I2C_FASTMODEPLUS_PA13) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PA14) == I2C_FASTMODEPLUS_PA14) ) +#endif /** * @} */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2s.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2s.h index 0e7ccecc5e..5ccbc3daa0 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2s.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2s.h @@ -27,7 +27,6 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32wl3x_hal_def.h" -#if defined(SPI_I2S_SUPPORT) /** @addtogroup STM32WL3x_HAL_Driver * @{ */ @@ -452,8 +451,8 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); * @{ */ /* Peripheral Control and State functions ************************************/ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); +HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s); /** * @} */ @@ -544,7 +543,6 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); /** * @} */ -#endif /* SPI_I2S_SUPPORT */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_mrsubg.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_mrsubg.h index ecc12acad2..4415cc8570 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_mrsubg.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_mrsubg.h @@ -76,6 +76,7 @@ extern "C" { * @{ */ + /** * @brief Send a specific command to the STM32WL3x. * @param __CMD_NAME__ code of the command to send. @@ -276,7 +277,7 @@ extern "C" { */ #define __HAL_MRSUBG_WMBUS_ENABLE_AND_SQI_MASK() \ { \ - CLEAR_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_nAND_SELECT); \ + CLEAR_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_NAND_SELECT); \ SET_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_SQI_TIMEOUT_MASK); \ } @@ -468,45 +469,236 @@ typedef struct /** @defgroup MRSUBG_Exported_Functions MRSUBG Exported Functions * @{ */ + +/** + * @brief Initialize the low-level hardware (MSP) for MRSubG. + * @retval None + */ void HAL_MRSubG_MspInit(void); +/** + * @brief De-initialize the low-level hardware (MSP) for MRSubG. + * @retval None + */ void HAL_MRSubG_MspDeInit(void); +/** + * @brief IRQ callback for MRSubG events. + * @retval None + */ void HAL_MRSubG_IRQ_Callback(void); +/** + * @brief BUSY callback for MRSubG events. + * @retval None + */ void HAL_MRSubG_BUSY_Callback(void); +/** + * @brief TX/RX sequence callback for MRSubG events. + * @retval None + */ void HAL_MRSubG_TX_RX_SEQUENCE_Callback(void); +/** + * @brief Wakeup callback for MRSubG events. + * @retval None + */ void HAL_MRSubG_WKUP_Callback(void); +/** + * @brief IRQ handler for MRSubG. + * @retval None + */ void HAL_MRSubG_IRQHandler(void); +/** + * @brief BUSY IRQ handler for MRSubG. + * @retval None + */ void HAL_MRSubG_BUSY_IRQHandler(void); +/** + * @brief TX/RX sequence IRQ handler for MRSubG. + * @retval None + */ void HAL_MRSubG_TX_RX_SEQUENCE_IRQHandler(void); +/** + * @brief Wakeup IRQ handler for MRSubG. + * @retval None + */ void HAL_MRSubG_WKUP_IRQHandler(void); +/** + * @brief Get the MRSubG IP version. + * @retval Version struct with product, version, and revision fields. + */ SMRSubGVersion_t HAL_MRSubGGetVersion(void); +/** + * @brief Initialize the MRSubG radio interface according to the specified parameters. + * @param pxSRadioInitStruct Pointer to a SMRSubGConfig_t structure with configuration info. + * @retval 0 if OK, 1 if error during VCO calibration. + */ uint8_t HAL_MRSubG_Init(SMRSubGConfig_t *pxSRadioInitStruct); +/** + * @brief Get the current radio configuration. + * @param pxSRadioInitStruct Pointer to a SMRSubGConfig_t structure to fill. + * @retval None + */ void HAL_MRSubG_GetInfo(SMRSubGConfig_t *pxSRadioInitStruct); +/** + * @brief Set the base carrier frequency. + * @param lFBase Base carrier frequency in Hz. + * @retval None + */ void HAL_MRSubG_SetFrequencyBase(uint32_t lFBase); +/** + * @brief Get the base carrier frequency. + * @retval Base carrier frequency in Hz. + */ uint32_t HAL_MRSubG_GetFrequencyBase(void); +/** + * @brief Set the datarate. + * @param lDatarate Datarate in sps. + * @retval None + */ void HAL_MRSubG_SetDatarate(uint32_t lDatarate); +/** + * @brief Get the datarate. + * @retval Datarate in sps. + */ uint32_t HAL_MRSubG_GetDatarate(void); +/** + * @brief Set the frequency deviation. + * @param lFDev Frequency deviation in Hz. + * @retval None + */ void HAL_MRSubG_SetFrequencyDev(uint32_t lFDev); +/** + * @brief Get the frequency deviation. + * @retval Frequency deviation in Hz. + */ uint32_t HAL_MRSubG_GetFrequencyDev(void); +#if defined(IS_169MHZ) +/** + * @brief Prepare the radio configuration for 169 MHz TX operations. + * Restores the base frequency to the default configuration and + * adjusts the frequency deviation for 169 MHz transmission. + * @retval None. + */ +void HAL_MRSubG_169MHz_prepareTx(void); +/** + * @brief Prepare the radio configuration for 169 MHz RX operations. + * Restores the frequency deviation to the default configuration and + * adjusts the base frequency for 169 MHz reception. + * @retval None. + */ +void HAL_MRSubG_169MHz_prepareRx(void); +#endif /* IS_169MHZ && GENERATOR_STM32WL3X */ +/** + * @brief Set the channel filter bandwidth. + * @param lBandwidth Channel filter bandwidth in Hz. + * @retval None + */ void HAL_MRSubG_SetChannelBW(uint32_t lBandwidth); +/** + * @brief Get the channel filter bandwidth. + * @retval Channel filter bandwidth in Hz. + */ uint32_t HAL_MRSubG_GetChannelBW(void); +/** + * @brief Set the modulation type and DSSS exponent. + * @param xModulation Modulation type. + * @param dsssExponent DSSS spreading exponent (0 = disabled). + * @retval None + */ void HAL_MRSubG_SetModulation(MRSubGModSelect xModulation, uint8_t dsssExponent); +/** + * @brief Get the modulation type. + * @retval Modulation type. + */ MRSubGModSelect HAL_MRSubG_GetModulation(void); +/** + * @brief Get the RSSI value in dBm. + * @retval RSSI value in dBm. + */ int32_t HAL_MRSubG_GetRssidBm(void); +/** + * @brief Set the RSSI threshold in dBm. + * @param rssiTh RSSI threshold in dBm. + * @retval None + */ void HAL_MRSubG_SetRSSIThreshold(int16_t rssiTh); +/** + * @brief Get the RSSI threshold in dBm. + * @retval RSSI threshold in dBm. + */ int32_t HAL_MRSubG_GetRSSIThreshold(void); +/** + * @brief Set the PA output power level in dBm. + * @param cIndex PA_LEVEL index [0:7]. + * @param lPowerdBm Output power in dBm. + * @param drvMode PA drive mode. + * @retval None + */ void HAL_MRSubG_SetPALeveldBm(uint8_t cIndex, int8_t lPowerdBm, MRSubG_PA_DRVMode drvMode); +/** + * @brief Get the PA output power level in dBm. + * @retval Output power in dBm. + */ int8_t HAL_MRSubG_GetPALeveldBm(void); +/** + * @brief Get the number of bytes after each TX/RX transaction. + * @retval Number of bytes. + */ uint32_t HAL_MRSubG_GetBytesOfTransaction(void); +/** + * @brief Convert microseconds to sequencer absolute time units. + * @param microseconds Time in microseconds. + * @retval Absolute time units. + */ uint32_t HAL_MRSubG_Sequencer_Microseconds(uint32_t microseconds); +/** + * @brief Convert milliseconds to sequencer absolute time units. + * @param milliseconds Time in milliseconds. + * @retval Absolute time units. + */ uint32_t HAL_MRSubG_Sequencer_Milliseconds(uint32_t milliseconds); +/** + * @brief Convert seconds to sequencer absolute time units. + * @param seconds Time in seconds. + * @retval Absolute time units. + */ uint32_t HAL_MRSubG_Sequencer_Seconds(uint32_t seconds); +/** + * @brief Store static configuration registers to sequencer global config table. + * @param cfg Pointer to global configuration table struct. + * @retval SUCCESS or ERROR. + */ ErrorStatus HAL_MRSubG_Sequencer_ApplyStaticConfig(MRSubG_Sequencer_GlobalConfiguration_t *cfg); +/** + * @brief Store dynamic configuration registers to sequencer action config table. + * @param cfg Pointer to action configuration table struct. + * @param cmd Command to issue for this action. + * @retval SUCCESS or ERROR. + */ ErrorStatus HAL_MRSubG_Sequencer_ApplyDynamicConfig(MRSubG_Sequencer_ActionConfiguration_t *cfg, MRSubGCmd cmd); +/** + * @brief Set the payload length for Basic packet format. + * @param nPayloadLength Payload length in bytes. + * @retval None + */ void HAL_MRSubG_PktBasicSetPayloadLength(uint16_t nPayloadLength); +/** + * @brief Initialize the Basic packet format. + * @param pxPktBasicInit Pointer to Basic packet init structure. + * @retval None + */ void HAL_MRSubG_PacketBasicInit(MRSubG_PcktBasicFields_t *pxPktBasicInit); +/** + * @brief Initialize the WMBUS packet format. + * @param pxPktWMbusInit Pointer to WMBUS packet init structure. + * @retval None + */ void HAL_MRSubG_WMBus_PacketInit(MRSubG_WMBUS_PcktFields_t *pxPktWMbusInit); +/** + * @brief Initialize the 802.15.4 packet format. + * @param px802_15_4PktInit Pointer to 802.15.4 packet init structure. + * @retval None + */ void HAL_MRSubG_802_15_4_PacketInit(MRSubG_802_15_4_PcktFields_t *px802_15_4PktInit); /** diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_mrsubg_timer.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_mrsubg_timer.h index b34fb5db33..c18f96422b 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_mrsubg_timer.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_mrsubg_timer.h @@ -22,7 +22,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* __cplusplus */ /* Includes ------------------------------------------------------------------*/ #include @@ -264,6 +264,6 @@ void HAL_MRSUBG_TIMER_MspDeInit(void); #ifdef __cplusplus } -#endif +#endif /* __cplusplus */ #endif /*STM32WL3x_HAL_MRSUBG_TIMER_H */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_rcc_ex.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_rcc_ex.h index 20a748faac..b7b47fe424 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_rcc_ex.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_rcc_ex.h @@ -103,8 +103,8 @@ typedef struct uint32_t SPI3I2SClockSelection; /*!< Specifies SPI3_I2S clock source. This parameter can be a value of @ref RCCEx_SPI3_I2S_Clock_Source */ - uint32_t RTCWDGSUBGLPAWURLCDLCSCClockSelection; /*!< Specifies RTC, WDG and BLEWKUP clock source. - This parameter can be a value of @ref RCCEx_RTC_WDG_BLEWKUP_Clock_Source */ + uint32_t RTCWDGSUBGLPAWURLCDLCSCClockSelection; /*!< Specifies RTC, WDG and SUBG clock source. + This parameter can be a value of @ref RCCEx_RTC_WDG_SUBG_Clock_Source */ #if defined(RCC_CFGR_LPUCLKSEL) uint32_t LPUART1ClockSelection; /*!< Specifies LPUART1 clock source. @@ -196,12 +196,12 @@ typedef struct /** * @} */ -/** @defgroup RCCEx_RTC_WDG_BLEWKUP_Clock_Source RTC, WDG, BLEWKUP Clock Source +/** @defgroup RCCEx_RTC_WDG_SUBG_Clock_Source RTC, WDG, SUBG Clock Source * @{ */ -#define RCC_RTC_WDG_SUBG_LPAWUR_LCD_LCSC_CLKSOURCE_LSE LL_RCC_LSCO_CLKSOURCE_LSE /*!< RTC, WDG and BLEWKUP LSE clock source selection */ -#define RCC_RTC_WDG_SUBG_LPAWUR_LCD_LCSC_CLKSOURCE_LSI LL_RCC_LSCO_CLKSOURCE_LSI /*!< RTC, WDG and BLEWKUP LSI clock source selection */ -#define RCC_RTC_WDG_SUBG_LPAWUR_LCD_LCSC_CLKSOURCE_DIV512 LL_RCC_LSCO_CLKSOURCE_HSI64M_DIV2048 /*!< RTC, WDG and BLEWKUP 32K clock source selection */ +#define RCC_RTC_WDG_SUBG_LPAWUR_LCD_LCSC_CLKSOURCE_LSE LL_RCC_LSCO_CLKSOURCE_LSE /*!< RTC, WDG and SUBG LSE clock source selection */ +#define RCC_RTC_WDG_SUBG_LPAWUR_LCD_LCSC_CLKSOURCE_LSI LL_RCC_LSCO_CLKSOURCE_LSI /*!< RTC, WDG and SUBG LSI clock source selection */ +#define RCC_RTC_WDG_SUBG_LPAWUR_LCD_LCSC_CLKSOURCE_DIV512 LL_RCC_LSCO_CLKSOURCE_HSI64M_DIV2048 /*!< RTC, WDG and SUBG 32K clock source selection */ /** * @} diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_smbus_ex.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_smbus_ex.h index 873d037138..b0e847ba23 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_smbus_ex.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_smbus_ex.h @@ -114,23 +114,33 @@ void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); /** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros * @{ */ -#if defined(I2C1) +#if defined(I2C1) && defined(I2C2) #define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ( \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6)) == SMBUS_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7)) == SMBUS_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA0)) == SMBUS_FASTMODEPLUS_PA0) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA1)) == SMBUS_FASTMODEPLUS_PA1) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB10)) == SMBUS_FASTMODEPLUS_PB10) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB11)) == SMBUS_FASTMODEPLUS_PB11) ) -#endif /* I2C1 */ - -#if defined(I2C2) + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PB6) == SMBUS_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PB7) == SMBUS_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PA0) == SMBUS_FASTMODEPLUS_PA0) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PA1) == SMBUS_FASTMODEPLUS_PA1) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PB10) == SMBUS_FASTMODEPLUS_PB10) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PB11) == SMBUS_FASTMODEPLUS_PB11) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PA6) == SMBUS_FASTMODEPLUS_PA6) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PA7) == SMBUS_FASTMODEPLUS_PA7) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PA13) == SMBUS_FASTMODEPLUS_PA13) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PA14) == SMBUS_FASTMODEPLUS_PA14) ) +#elif defined(I2C1) #define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ( \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA6)) == SMBUS_FASTMODEPLUS_PA6) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA7)) == SMBUS_FASTMODEPLUS_PA7) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA13)) == SMBUS_FASTMODEPLUS_PA13) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA14)) == SMBUS_FASTMODEPLUS_PA14) ) -#endif /* I2C2 */ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PB6) == SMBUS_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PB7) == SMBUS_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PA0) == SMBUS_FASTMODEPLUS_PA0) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PA1) == SMBUS_FASTMODEPLUS_PA1) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PB10) == SMBUS_FASTMODEPLUS_PB10) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PB11) == SMBUS_FASTMODEPLUS_PB11) ) +#elif defined(I2C2) +#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ( \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PA6) == SMBUS_FASTMODEPLUS_PA6) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PA7) == SMBUS_FASTMODEPLUS_PA7) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PA13) == SMBUS_FASTMODEPLUS_PA13) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PA14) == SMBUS_FASTMODEPLUS_PA14) ) +#endif /** * @} diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_spi.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_spi.h index 7eb63e1a07..fb6e378c79 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_spi.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_spi.h @@ -118,7 +118,7 @@ typedef struct __SPI_HandleTypeDef SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size */ @@ -426,11 +426,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval None */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ @@ -533,7 +534,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to __IO uint32_t tmpreg_fre = 0x00U; \ tmpreg_fre = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg_fre); \ - }while(0U) + } while(0U) /** @brief Enable the SPI peripheral. * @param __HANDLE__ specifies the SPI Handle. @@ -577,8 +578,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ - SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) +#define SPI_RESET_CRC(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + } while(0U) /** @brief Check whether the specified SPI flag is set or not. * @param __SR__ copy of SPI SR register. @@ -596,7 +600,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ - ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. * @param __CR2__ copy of SPI CR2 register. @@ -608,7 +612,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ - (__INTERRUPT__)) ? SET : RESET) + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. @@ -746,7 +750,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ ((__POLYNOMIAL__) <= 0xFFFFU) && \ - (((__POLYNOMIAL__)&0x1U) != 0U)) + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. @@ -789,17 +793,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); @@ -825,8 +829,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); /** * @} */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_uart.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_uart.h index 4964103906..64d42c21a0 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_uart.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_uart.h @@ -1285,7 +1285,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) * divided by the smallest oversampling used on the USART (i.e. 8) * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ -#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 2000001U) +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 2000000U) /** @brief Check UART assertion time. * @param __TIME__ 5-bit value assertion time. diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h index e49d7c53f5..b94790b322 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h @@ -433,7 +433,6 @@ typedef struct */ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } @@ -454,7 +453,6 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } @@ -475,7 +473,6 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); } @@ -512,7 +509,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, Configuration); @@ -540,7 +536,6 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); } @@ -566,7 +561,6 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM)); } @@ -593,7 +587,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint */ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC, Mode); } @@ -617,7 +610,6 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_ */ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC)); } @@ -642,7 +634,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC, PeriphOrM2MSrcIncMode); } @@ -666,7 +657,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC)); } @@ -691,7 +681,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC, MemoryOrM2MDstIncMode); } @@ -715,7 +704,6 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC)); } @@ -741,7 +729,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE, PeriphOrM2MSrcDataSize); } @@ -766,7 +753,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE)); } @@ -792,7 +778,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE, MemoryOrM2MDstDataSize); } @@ -817,7 +802,6 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE)); } @@ -844,7 +828,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL, Priority); } @@ -870,7 +853,6 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL)); } @@ -895,7 +877,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint3 */ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR, DMA_CNDTR_NDT, NbData); } @@ -919,7 +900,6 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR, DMA_CNDTR_NDT)); } @@ -951,7 +931,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { - (void)DMAx; /* Direction Memory to Periph */ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) { @@ -986,7 +965,6 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } @@ -1010,7 +988,6 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) { - (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress); } @@ -1032,7 +1009,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } @@ -1054,7 +1030,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } @@ -1078,7 +1053,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress); } @@ -1102,7 +1076,6 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } @@ -1124,7 +1097,6 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } @@ -1146,7 +1118,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } @@ -1169,7 +1140,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID, Request); } @@ -1191,7 +1161,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID)); } @@ -1211,7 +1180,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); } @@ -1223,7 +1191,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); } @@ -1235,7 +1202,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); } @@ -1247,7 +1213,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); } @@ -1259,7 +1224,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); } @@ -1271,7 +1235,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); } @@ -1283,7 +1246,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); } @@ -1295,7 +1257,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF8) == (DMA_ISR_GIF8)) ? 1UL : 0UL); } @@ -1307,7 +1268,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); } @@ -1319,7 +1279,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); } @@ -1331,7 +1290,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); } @@ -1343,7 +1301,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); } @@ -1355,7 +1312,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); } @@ -1367,7 +1323,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); } @@ -1379,7 +1334,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); } @@ -1391,7 +1345,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF8) == (DMA_ISR_TCIF8)) ? 1UL : 0UL); } @@ -1403,7 +1356,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); } @@ -1415,7 +1367,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); } @@ -1427,7 +1378,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); } @@ -1439,7 +1389,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); } @@ -1451,7 +1400,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); } @@ -1463,7 +1411,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); } @@ -1475,7 +1422,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); } @@ -1487,7 +1433,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF8) == (DMA_ISR_HTIF8)) ? 1UL : 0UL); } @@ -1499,7 +1444,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); } @@ -1511,7 +1455,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); } @@ -1523,7 +1466,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); } @@ -1535,7 +1477,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); } @@ -1547,7 +1488,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); } @@ -1559,7 +1499,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); } @@ -1571,7 +1510,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); } @@ -1583,7 +1521,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF8) == (DMA_ISR_TEIF8)) ? 1UL : 0UL); } @@ -1595,7 +1532,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); } @@ -1607,7 +1543,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); } @@ -1619,7 +1554,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); } @@ -1631,7 +1565,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); } @@ -1643,7 +1576,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); } @@ -1655,7 +1587,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); } @@ -1667,7 +1598,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); } @@ -1679,7 +1609,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF8); } @@ -1691,7 +1620,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); } @@ -1703,7 +1631,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); } @@ -1715,7 +1642,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); } @@ -1727,7 +1653,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); } @@ -1739,7 +1664,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); } @@ -1751,7 +1675,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); } @@ -1763,7 +1686,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); } @@ -1775,7 +1697,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF8); } @@ -1787,7 +1708,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); } @@ -1799,7 +1719,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); } @@ -1811,7 +1730,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); } @@ -1823,7 +1741,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); } @@ -1835,7 +1752,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); } @@ -1847,7 +1763,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); } @@ -1859,7 +1774,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); } @@ -1871,7 +1785,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF8); } @@ -1883,7 +1796,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); } @@ -1895,7 +1807,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); } @@ -1907,7 +1818,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); } @@ -1919,7 +1829,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); } @@ -1931,7 +1840,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); } @@ -1943,7 +1851,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); } @@ -1955,7 +1862,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); } @@ -1967,7 +1873,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF8); } @@ -1995,7 +1900,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } @@ -2016,7 +1920,6 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } @@ -2037,7 +1940,6 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } @@ -2058,7 +1960,6 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } @@ -2079,7 +1980,6 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } @@ -2100,7 +2000,6 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } @@ -2121,7 +2020,6 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); } @@ -2143,7 +2041,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); } @@ -2165,7 +2062,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_gpio.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_gpio.h index 97d069d59a..5319a172b8 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_gpio.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_gpio.h @@ -910,7 +910,7 @@ __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMas __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { uint32_t odr = READ_REG(GPIOx->ODR); - WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16U) | (~odr & PinMask)); } /** diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_mrsubg.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_mrsubg.h index 87bced5968..6e270ed073 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_mrsubg.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_mrsubg.h @@ -41,37 +41,44 @@ extern "C" { */ /* Legacy aliases */ + #if defined(IS_169MHZ) -#define STM32WL33XA +/*Check compatible board*/ +#if !defined(STM32WL33XA) +#error "IS_169MHZ is defined but no compatible board is selected. Add STM32WL33XA or extend the mapping for new boards." +#endif /* !STM32WL33XA */ #endif /* IS_169MHZ */ #if defined(STM32WL33XA) + /* WL33xA */ -#define LOW_BAND_FACTOR 20 /*!< Band select factor for middle band. Factor B in the equation of the user manual */ -#define HIGH_BAND_FACTOR 8 /*!< Band select factor for high band. Factor B in the equation of the user manual */ - -#define LOW_BAND_LOWER_LIMIT 159200000 /*!< Lower limit of the low band */ -#define LOW_BAND_UPPER_LIMIT 185600000 /*!< Upper limit of the low band */ -#define HIGH_BAND_LOWER_LIMIT 398000000 /*!< Lower limit of the high band */ -#define HIGH_BAND_UPPER_LIMIT 464000000 /*!< Upper limit of the high band */ -#else -#if defined(STM32WL3RX) -/* WL3x including WL3Rx at 315 MHz */ -#define LOW_LOW_BAND_FACTOR 12 /*!< Band select factor for middle band. Factor B in the equation of the user manual */ -#endif /* STM32WL3RX */ +#define LOW_BAND_FACTOR 20 /*!< Band select factor for middle band. Factor B in the equation of the user manual */ +#define HIGH_BAND_FACTOR 8 /*!< Band select factor for high band. Factor B in the equation of the user manual */ + +#define LOW_BAND_LOWER_LIMIT 159200000 /*!< Lower limit of the low band */ +#define LOW_BAND_UPPER_LIMIT 185600000 /*!< Upper limit of the low band */ +#define HIGH_BAND_LOWER_LIMIT 398000000 /*!< Lower limit of the high band */ +#define HIGH_BAND_UPPER_LIMIT 464000000 /*!< Upper limit of the high band */ + +#else /* !STM32WL33XA */ -#define LOW_BAND_FACTOR 8 /*!< Band select factor for middle band. Factor B in the equation of the user manual */ -#define HIGH_BAND_FACTOR 4 /*!< Band select factor for high band. Factor B in the equation of the user manual */ +/* Common values for all other boards */ +#define LOW_BAND_FACTOR 8 /*!< Band select factor for middle band. Factor B in the equation of the user manual */ +#define HIGH_BAND_FACTOR 4 /*!< Band select factor for high band. Factor B in the equation of the user manual */ + +#define LOW_BAND_LOWER_LIMIT 413000000 /*!< Lower limit of the low band */ +#define LOW_BAND_UPPER_LIMIT 479000000 /*!< Upper limit of the low band */ +#define HIGH_BAND_LOWER_LIMIT 826000000 /*!< Lower limit of the high band */ +#define HIGH_BAND_UPPER_LIMIT 958000000 /*!< Upper limit of the high band */ #if defined(STM32WL3RX) -#define LOW_LOW_BAND_LOWER_LIMIT 275500000 /*!< Lower limit of the low low band */ -#define LOW_LOW_BAND_UPPER_LIMIT 318500000 /*!< Upper limit of the low low band */ +/* WL3x including WL3Rx at 315 MHz: adds low-low band support */ +#define LOW_LOW_BAND_FACTOR 12 /*!< Band select factor for low-low band. Factor B in the equation of the user manual */ + +#define LOW_LOW_BAND_LOWER_LIMIT 275500000 /*!< Lower limit of the low-low band */ +#define LOW_LOW_BAND_UPPER_LIMIT 318500000 /*!< Upper limit of the low-low band */ #endif /* STM32WL3RX */ -#define LOW_BAND_LOWER_LIMIT 413000000 /*!< Lower limit of the low band */ -#define LOW_BAND_UPPER_LIMIT 479000000 /*!< Upper limit of the low band */ -#define HIGH_BAND_LOWER_LIMIT 826000000 /*!< Lower limit of the high band */ -#define HIGH_BAND_UPPER_LIMIT 958000000 /*!< Upper limit of the high band */ #endif /* STM32WL33XA */ #define MINIMUM_DATARATE 100 /*!< Minimum datarate supported by STM32WL3x 100 bps */ @@ -119,6 +126,7 @@ then a match can never occur because SEQ_F is only set when the sequencer termin #define PREAMBLE_BYTE(v) (4*v) #define SYNC_BYTE(v) ((8*v)-1) +#define MRSUBG_RADIO_SYNTH0_ANA_ENG_REG (*((__IO uint32_t *)((uint32_t)MR_SUBG_RADIO + 0xC0U))) /** * @} */ @@ -272,6 +280,42 @@ typedef enum demodulator (soft bits before the 0/1 detection) are stored in RAM. */ } MRSubGRXMode; +/** + * @brief STM32WL3x PA CFG Filtering + */ +typedef enum +{ + FILTERING = 0x00, /*!< 00: filtering */ + RAMPING = 0x01, /*!< 01: ramping */ + SWITCHING = 0x02 /*!< 10: switching */ +} MRSubGPaCfgFilt; + +/** + * @brief STM32WL3x RX PGA attenuation (RFD_RX_PGA_AGCGAIN[2:0]) - 6 dB steps, binary code. + */ +typedef enum +{ + AGC_PGA_ATTEN_0dB = 0x0U, /*!< 000: 0 dB */ + AGC_PGA_ATTEN_6dB = 0x1U, /*!< 001: -6 dB */ + AGC_PGA_ATTEN_12dB = 0x2U, /*!< 010: -12 dB */ + AGC_PGA_ATTEN_18dB = 0x3U, /*!< 011: -18 dB */ + AGC_PGA_ATTEN_24dB = 0x4U, /*!< 100: -24 dB */ + AGC_PGA_ATTEN_30dB = 0x5U /*!< 101: -30 dB */ +} MRSubGAgcPgaAtten; + +/** + * @brief STM32WL3x RX LNA attenuation (RFD_RX_ATTEN_AGCGAIN[3:0]) - 6 dB steps, thermometric code. + */ +typedef enum +{ + AGC_LNA_ATTEN_0dB = 0x0U, /*!< 0000: 0 dB */ + AGC_LNA_ATTEN_6dB = 0x1U, /*!< 0001: -6 dB */ + AGC_LNA_ATTEN_12dB = 0x3U, /*!< 0011: -12 dB */ + AGC_LNA_ATTEN_18dB = 0x7U, /*!< 0111: -18 dB */ + AGC_LNA_ATTEN_24dB = 0xFU /*!< 1111: -24 dB */ +} MRSubGAgcLnaAtten; + + /** * @brief STM32WL3x preamble pattern enumeration */ @@ -339,10 +383,10 @@ typedef enum PKT_CRC_MODE_8BITS = 0x01, /*!< CRC length 8 bits - poly: 0x07 */ PKT_CRC_MODE_16BITS_1 = 0x02, /*!< CRC length 16 bits - poly: 0x8005 */ PKT_CRC_MODE_16BITS_2 = 0x03, /*!< CRC length 16 bits - poly: 0x1021 */ - FCS_16BIT = 0x03, /*!< CRC length 16 bits - poly: 0x1021 */ + FCS_16BIT = 0x03, /*!< CRC length 16 bits - poly: 0x1021 */ PKT_CRC_MODE_24BITS = 0x04, /*!< CRC length 24 bits - poly: 0x864CFB */ PKT_CRC_MODE_32BITS = 0x05, /*!< CRC length 32 bits - poly: 0x04C11DB7 */ - FCS_32BIT = 0x05, /*!< CRC length 32 bits - poly: 0x04C11DB7 */ + FCS_32BIT = 0x05, /*!< CRC length 32 bits - poly: 0x04C11DB7 */ } MRSubG_PcktCrcMode; /** @@ -597,7 +641,31 @@ __STATIC_INLINE void LL_MRSubG_SetISIEqualizer(MRSubG_ISIEQMode isiEq) */ __STATIC_INLINE void LL_MRSubG_StrobeCommand(MRSubGCmd xCommandCode) { - MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->COMMAND, MR_SUBG_GLOB_DYNAMIC_COMMAND_COMMAND_ID, xCommandCode); + if ((xCommandCode == CMD_TX) || (xCommandCode == CMD_RX) || + (xCommandCode == CMD_LOCKRX) || (xCommandCode == CMD_LOCKTX)) + { + volatile uint32_t __mrsubg_delay; + uint32_t command_reg_backup = READ_REG(MR_SUBG_GLOB_DYNAMIC->COMMAND); + + WRITE_REG(MR_SUBG_GLOB_DYNAMIC->COMMAND, + (command_reg_backup & MR_SUBG_GLOB_DYNAMIC_COMMAND_BACK2LOCKON) | + MR_SUBG_GLOB_DYNAMIC_COMMAND_BACK2ACTIVE | + CMD_NOP); + WRITE_REG(MRSUBG_RADIO_SYNTH0_ANA_ENG_REG, 0x87U); + WRITE_REG(MR_SUBG_GLOB_DYNAMIC->COMMAND, + (command_reg_backup & ~MR_SUBG_GLOB_DYNAMIC_COMMAND_COMMAND_ID) | xCommandCode); + + for (__mrsubg_delay = 0U; __mrsubg_delay < 3U; __mrsubg_delay++) + { + __NOP(); + } + + WRITE_REG(MRSUBG_RADIO_SYNTH0_ANA_ENG_REG, 0x07U); + } + else + { + MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->COMMAND, MR_SUBG_GLOB_DYNAMIC_COMMAND_COMMAND_ID, xCommandCode); + } } /** @@ -686,6 +754,123 @@ __STATIC_INLINE void LL_MRSubG_SetPADegen(FunctionalState xNewState) } } +/** + * @brief Get the PA_DEGEN_ON bit state. + * @retval ENABLE if degeneration mode is enabled, + * DISABLE otherwise. + */ +__STATIC_INLINE FunctionalState LL_MRSubG_GetPADegen(void) +{ + return (READ_BIT(MR_SUBG_RADIO->PA_REG, MR_SUBG_RADIO_PA_REG_PA_DEGEN_ON) != 0U) + ? ENABLE : DISABLE; +} + +/** + * @brief Set the PA FIR configuration (CFG_FILT[1:0]). + * This field selects the PA filtering mode: + * - 00: filtering + * - 01: ramping + * - 10: switching + * @param mode PA configuration value of type @ref MRSubGPaCfgFilt. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetPaCfgFilt(MRSubGPaCfgFilt mode) +{ + MODIFY_REG(MR_SUBG_RADIO->PA_REG, MR_SUBG_RADIO_PA_REG_CFG_FILT_Msk, + (mode << MR_SUBG_RADIO_PA_REG_CFG_FILT_Pos)); +} + +/** + * @brief Get the PA FIR configuration (CFG_FILT[1:0]). + * @retval PA configuration value of type @ref MRSubGPaCfgFilt. + */ +__STATIC_INLINE MRSubGPaCfgFilt LL_MRSubG_GetPaCfgFilt(void) +{ + return (MRSubGPaCfgFilt)((READ_REG(MR_SUBG_RADIO->PA_REG) & + MR_SUBG_RADIO_PA_REG_CFG_FILT_Msk) >> + MR_SUBG_RADIO_PA_REG_CFG_FILT_Pos); +} + +/** + * @brief Enable/Disable AGC analog test mode (FORCE_AGC_GAINS). + * 0: gains controlled by AGC controller. + * 1: gains forced by AGC_ANA_ENG register fields. + * @param state ENABLE to force gains, DISABLE for normal AGC control. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetAgcForceGains(FunctionalState state) +{ + if (state == ENABLE) + { + SET_BIT(MR_SUBG_RADIO->AGC_ANA_ENG, MR_SUBG_RADIO_AGC_ANA_ENG_FORCE_AGC_GAINS); + } + else + { + CLEAR_BIT(MR_SUBG_RADIO->AGC_ANA_ENG, MR_SUBG_RADIO_AGC_ANA_ENG_FORCE_AGC_GAINS); + } +} + +/** + * @brief Get AGC analog test mode state (FORCE_AGC_GAINS). + * @retval ENABLE if gains are forced by AGC_ANA_ENG, + * DISABLE if gains are controlled by AGC controller. + */ +__STATIC_INLINE FunctionalState LL_MRSubG_GetAgcForceGains(void) +{ + return (READ_BIT(MR_SUBG_RADIO->AGC_ANA_ENG, + MR_SUBG_RADIO_AGC_ANA_ENG_FORCE_AGC_GAINS) != 0U) + ? ENABLE : DISABLE; +} + +/** + * @brief Set RX PGA attenuation (RFD_RX_PGA_AGCGAIN[2:0]). + * @param atten Value from @ref MRSubGAgcPgaAtten. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetAgcPgaAtten(MRSubGAgcPgaAtten atten) +{ + MODIFY_REG(MR_SUBG_RADIO->AGC_ANA_ENG, + MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_PGA_AGCGAIN_Msk, + atten << MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_PGA_AGCGAIN_Pos); +} + +/** + * @brief Get RX PGA attenuation (RFD_RX_PGA_AGCGAIN[2:0]). + * @retval Value from @ref MRSubGAgcPgaAtten. + */ +__STATIC_INLINE MRSubGAgcPgaAtten LL_MRSubG_GetAgcPgaAtten(void) +{ + return (MRSubGAgcPgaAtten) + ((READ_REG(MR_SUBG_RADIO->AGC_ANA_ENG) & + MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_PGA_AGCGAIN_Msk) >> + MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_PGA_AGCGAIN_Pos); +} + +/** + * @brief Set RX LNA attenuation (RFD_RX_ATTEN_AGCGAIN[3:0]). + * Thermometric code in 6 dB steps. + * @param atten Value from @ref MRSubGAgcLnaAtten. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetAgcLnaAtten(MRSubGAgcLnaAtten atten) +{ + MODIFY_REG(MR_SUBG_RADIO->AGC_ANA_ENG, + MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_ATTEN_AGCGAIN_Msk, + atten << MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_ATTEN_AGCGAIN_Pos); +} + +/** + * @brief Get RX LNA attenuation (RFD_RX_ATTEN_AGCGAIN[3:0]). + * @retval Value from @ref MRSubGAgcLnaAtten. + */ +__STATIC_INLINE MRSubGAgcLnaAtten LL_MRSubG_GetAgcLnaAtten(void) +{ + return (MRSubGAgcLnaAtten) + ((READ_REG(MR_SUBG_RADIO->AGC_ANA_ENG) & + MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_ATTEN_AGCGAIN_Msk) >> + MR_SUBG_RADIO_AGC_ANA_ENG_RFD_RX_ATTEN_AGCGAIN_Pos); +} + /** * @brief Returns the actual PA_LEVEL_MAX_INDEX. * @retval uint8_t Actual PA_LEVEL_MAX_INDEX. This parameter will be in the range [0:7]. @@ -1165,10 +1350,10 @@ __STATIC_INLINE void LL_MRSubG_SetRxOrnAndSelect(FlagStatus xNewState) { if (xNewState == SET) { - SET_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_nAND_SELECT); + SET_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_NAND_SELECT); } else - CLEAR_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_nAND_SELECT); + CLEAR_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_NAND_SELECT); } /** diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_pwr.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_pwr.h index 31fbb4b0c5..3c5d7d1053 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_pwr.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_pwr.h @@ -643,6 +643,156 @@ __STATIC_INLINE uint32_t LL_PWR_GetRAMBankRet(void) return (READ_BIT(PWR->CR2, PWR_CR2_RAMRET1) ? 1UL : 0UL); } +/** + * @brief Enable the RF Regulator. + * @rmtoll CR2 RFREGEN LL_PWR_EnableRFREGEN + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableRFREGEN(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_RFREGEN); +} + +/** + * @brief Disable the RF Regulator. + * @rmtoll CR2 RFREGEN LL_PWR_DisableRFREGEN + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableRFREGEN(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_RFREGEN); +} + +/** + * @brief Checks if RF regulator is enabled or disabled. + * @rmtoll CR2 RFREGEN LL_PWR_GetRFREGEN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_GetRFREGEN(void) +{ + return (READ_BIT(PWR->CR2, PWR_CR2_RFREGEN) ? 1UL : 0UL); +} + +/** + * @brief Enable the RF Regulator Bypass. + * @rmtoll CR2 RFREGBYP LL_PWR_EnableRFREGBYP + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableRFREGBYP(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_RFREGBYP); +} + +/** + * @brief Disable the RF Regulator Bypass. + * @rmtoll CR2 RFREGBYP LL_PWR_DisableRFREGBYP + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableRFREGBYP(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_RFREGBYP); +} + +/** + * @brief Checks if the RF Regulator Bypass is enabled or disabled. + * @rmtoll CR2 RFREGBYP LL_PWR_GetRFREGBYP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_GetRFREGBYP(void) +{ + return (READ_BIT(PWR->CR2, PWR_CR2_RFREGBYP) ? 1UL : 0UL); +} + +/** + * @brief Enable the RF Regulator External Supply Bypass capability. + * @rmtoll CR2 RFREGCEXT LL_PWR_EnableRFREGCEXT + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableRFREGCEXT(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_RFREGCEXT); +} + +/** + * @brief Disable the RF Regulator External Supply Bypass capability. + * @rmtoll CR2 RFREGCEXT LL_PWR_DisableRFREGCEXT + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableRFREGCEXT(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_RFREGCEXT); +} + +/** + * @brief Checks if the the RF Regulator External Supply Bypass capability. + * @rmtoll CR2 RFREGCEXT LL_PWR_GetRFREGCEXT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_GetRFREGCEXT(void) +{ + return (READ_BIT(PWR->CR2, PWR_CR2_RFREGCEXT) ? 1UL : 0UL); +} + +/** + * @brief Get the RF Regulator on status. + * @rmtoll CR2 RFREGON_STATUS LL_PWR_IsActiveFlag_RFREGON_STATUS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_RFREGON_STATUS(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_RFREGON_STATUS) == (PWR_CR2_RFREGON_STATUS)) ? 1UL : 0UL); +} + +/** + * @brief Get the RF Regulator ready flag. + * @rmtoll CR2 RFREGRDY LL_PWR_IsActiveFlag_RFREGRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_RFREGRDY(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_RFREGRDY) == (PWR_CR2_RFREGRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get the LPREG status. + * @rmtoll CR2 LPREG_VH_STATUS LL_PWR_IsActiveFlag_LPREG_VH_STATUS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_LPREG_VH_STATUS(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_LPREG_VH_STATUS) == (PWR_CR2_LPREG_VH_STATUS)) ? 1UL : 0UL); +} + +/** + * @brief Force the LPREG voltage to 1.2 V during Deepstop mode. + * @rmtoll CR2 LPREG_FORCE_VH LL_PWR_EnableLPREGVH + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableLPREGVH(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_LPREG_FORCE_VH); +} + +/** + * @brief Force the LPREG voltage to 1 V during Deepstop mode. + * @rmtoll CR2 LPREG_FORCE_VH LL_PWR_DisableLPREGVH + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableLPREGVH(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_LPREG_FORCE_VH); +} + +/** + * @brief Checks the LPREG voltage during Deepstop mode. + * @rmtoll CR2 LPREG_FORCE_VH LL_PWR_GetLPREGVH + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_GetLPREGVH(void) +{ + return (READ_BIT(PWR->CR2, PWR_CR2_LPREG_FORCE_VH) ? 1UL : 0UL); +} + /** * @brief Enable the PVD (Programmable Voltage Detector). * @rmtoll CR2 PVDE LL_PWR_EnablePVD @@ -1915,37 +2065,6 @@ __STATIC_INLINE uint32_t LL_PWR_GetMRTrim(void) } } -#if defined(PWR_ENGTRIM_TRIM_LSI_LPMU) -/** - * @brief Set Low Speed Internal oscillator LPMU trimming value. - * @rmtoll ENGTRIM LL_PWR_SetLPMULSITrim - * @param Trim Low Speed Internal oscillator trimming value - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetLSILPMUTrim(uint32_t Trim) -{ - MODIFY_REG(PWR->ENGTRIM, PWR_ENGTRIM_TRIM_LSI_LPMU, ((Trim << PWR_ENGTRIM_TRIM_LSI_LPMU_Pos) & PWR_ENGTRIM_TRIM_LSI_LPMU)); - SET_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIMLSILPMUEN); -} - -/** - * @brief Get Low Speed Internal oscillator LPMU trimming value. - * @rmtoll TRIMR/ENGTRIM LL_PWR_GetLSITrim - * @retval Low Speed Internal oscillator trimming value - */ -__STATIC_INLINE uint32_t LL_PWR_GetLSILPMUTrim(void) -{ - if (READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIMLSILPMUEN)) - { - return (uint32_t)(READ_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIM_LSI_LPMU) >> PWR_ENGTRIM_TRIM_LSI_LPMU_Pos); - } - else - { - return (uint32_t)(READ_BIT(PWR->TRIMR, PWR_TRIMR_TRIM_LSI_LPMU) >> PWR_TRIMR_TRIM_LSI_LPMU_Pos); - } -} -#endif /* PWR_ENGTRIM_TRIM_LSI_LPMU */ - #if defined(PWR_ENGTRIM_TRIM_RFDREG) /** * @brief Set RF LDO trimming value. diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_rcc.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_rcc.h index a92eb13aed..35792ff50e 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_rcc.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_rcc.h @@ -498,6 +498,38 @@ __STATIC_INLINE uint32_t LL_RCC_HSE_IsEnabled(void) return ((READ_BIT(RCC->CR, RCC_CR_HSEON) == (RCC_CR_HSEON)) ? 1UL : 0UL); } +/** + * @brief Select HSI as clock source for MRSUBG timer bit interpolation. + * (FMRAT = 1: MRSUBG timer uses HSI clock) + * @rmtoll CR FMRAT LL_RCC_FMRAT_UseHSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_FMRAT_UseHSI(void) +{ + SET_BIT(RCC->CR, RCC_CR_FMRAT); +} + +/** + * @brief Select HSE as clock source for MRSUBG timer bit interpolation. + * (FMRAT = 0: MRSUBG timer uses precise HSE clock) + * @rmtoll CR FMRAT LL_RCC_FMRAT_UseHSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_FMRAT_UseHSE(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_FMRAT); +} + +/** + * @brief Check if MRSUBG timer bit interpolation uses HSI clock. + * @rmtoll CR FMRAT LL_RCC_FMRAT_IsHSI + * @retval 1UL if FMRAT bit is set (HSI used), 0UL if clear (HSE used). + */ +__STATIC_INLINE uint32_t LL_RCC_FMRAT_IsHSI(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_FMRAT) == RCC_CR_FMRAT) ? 1UL : 0UL; +} + /** * @brief Check if HSE oscillator Ready * @rmtoll CR HSERDY LL_RCC_HSE_IsReady diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_spi.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_spi.h index 2941394eea..ae2f2f41bd 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_spi.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_spi.h @@ -55,53 +55,66 @@ typedef struct uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferDirection().*/ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). This parameter can be a value of @ref SPI_LL_EC_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetMode().*/ uint32_t DataWidth; /*!< Specifies the SPI data width. This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetDataWidth().*/ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_LL_EC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPolarity().*/ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_LL_EC_PHASE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPhase().*/ - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetNSSMode().*/ - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. The slave clock does not need to be set. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetBaudRatePrescaler().*/ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferBitOrder().*/ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. - This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + This feature can be modified afterwards using unitary + functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetCRCPolynomial().*/ } LL_SPI_InitTypeDef; @@ -378,7 +391,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); } @@ -408,7 +421,7 @@ __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_SPI_MODE_MASTER * @arg @ref LL_SPI_MODE_SLAVE */ -__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); } @@ -436,7 +449,7 @@ __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_SPI_PROTOCOL_MOTOROLA * @arg @ref LL_SPI_PROTOCOL_TI */ -__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); } @@ -465,7 +478,7 @@ __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase * @arg @ref LL_SPI_PHASE_1EDGE * @arg @ref LL_SPI_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); } @@ -494,7 +507,7 @@ __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_SPI_POLARITY_LOW * @arg @ref LL_SPI_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); } @@ -534,7 +547,7 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); } @@ -562,7 +575,7 @@ __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO * @arg @ref LL_SPI_LSB_FIRST * @arg @ref LL_SPI_MSB_FIRST */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); } @@ -599,7 +612,7 @@ __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t Tra * @arg @ref LL_SPI_HALF_DUPLEX_RX * @arg @ref LL_SPI_HALF_DUPLEX_TX */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); } @@ -648,7 +661,7 @@ __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) * @arg @ref LL_SPI_DATAWIDTH_15BIT * @arg @ref LL_SPI_DATAWIDTH_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); } @@ -675,7 +688,7 @@ __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Thres * @arg @ref LL_SPI_RX_FIFO_TH_HALF * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); } @@ -719,7 +732,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); } @@ -747,7 +760,7 @@ __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) * @arg @ref LL_SPI_CRC_8BIT * @arg @ref LL_SPI_CRC_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); } @@ -782,7 +795,7 @@ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->CRCPR)); } @@ -793,7 +806,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->RXCRCR)); } @@ -804,7 +817,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->TXCRCR)); } @@ -845,7 +858,7 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) * @arg @ref LL_SPI_NSS_HARD_INPUT * @arg @ref LL_SPI_NSS_HARD_OUTPUT */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) { uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); @@ -883,7 +896,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); } @@ -902,7 +915,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); } @@ -913,7 +926,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); } @@ -924,7 +937,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); } @@ -935,7 +948,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); } @@ -946,7 +959,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); } @@ -964,7 +977,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); } @@ -975,7 +988,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); } @@ -990,7 +1003,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_RX_FIFO_HALF_FULL * @arg @ref LL_SPI_RX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); } @@ -1005,7 +1018,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_TX_FIFO_HALF_FULL * @arg @ref LL_SPI_TX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); } @@ -1045,7 +1058,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->DR; @@ -1061,7 +1074,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -1078,7 +1091,8 @@ __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) /** * @brief Enable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1112,7 +1126,8 @@ __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) /** * @brief Disable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1150,7 +1165,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); } @@ -1161,7 +1176,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); } @@ -1172,7 +1187,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); } @@ -1213,7 +1228,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); } @@ -1246,7 +1261,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); } @@ -1273,7 +1288,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); } @@ -1300,7 +1315,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); } @@ -1311,7 +1326,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx) { return (uint32_t) &(SPIx->DR); } @@ -1388,7 +1403,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); @@ -1404,7 +1419,6 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); * @} */ -#if defined(SPI_I2S_SUPPORT) /** @defgroup I2S_LL I2S * @{ */ @@ -1656,7 +1670,7 @@ __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL); } @@ -1689,7 +1703,7 @@ __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat * @arg @ref LL_I2S_DATAFORMAT_24B * @arg @ref LL_I2S_DATAFORMAT_32B */ -__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); } @@ -1716,7 +1730,7 @@ __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_I2S_POLARITY_LOW * @arg @ref LL_I2S_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); } @@ -1751,7 +1765,7 @@ __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_I2S_STANDARD_PCM_SHORT * @arg @ref LL_I2S_STANDARD_PCM_LONG */ -__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); } @@ -1782,7 +1796,7 @@ __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_I2S_MODE_MASTER_TX * @arg @ref LL_I2S_MODE_MASTER_RX */ -__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); } @@ -1805,7 +1819,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t Presca * @param SPIx SPI Instance * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); } @@ -1832,7 +1846,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t Presc * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN * @arg @ref LL_I2S_PRESCALER_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); } @@ -1865,7 +1879,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL); } @@ -1899,7 +1913,7 @@ __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL); } @@ -1919,7 +1933,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_RXNE(SPIx); } @@ -1930,7 +1944,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_TXE(SPIx); } @@ -1941,7 +1955,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_BSY(SPIx); } @@ -1952,7 +1966,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_OVR(SPIx); } @@ -1963,7 +1977,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); } @@ -1974,7 +1988,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_FRE(SPIx); } @@ -1988,7 +2002,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL); } @@ -2010,7 +2024,7 @@ __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -2023,7 +2037,7 @@ __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(const SPI_TypeDef *SPIx) { LL_SPI_ClearFlag_FRE(SPIx); } @@ -2110,7 +2124,7 @@ __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_ERR(SPIx); } @@ -2121,7 +2135,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_RXNE(SPIx); } @@ -2132,7 +2146,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_TXE(SPIx); } @@ -2173,7 +2187,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledDMAReq_RX(SPIx); } @@ -2206,7 +2220,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledDMAReq_TX(SPIx); } @@ -2251,7 +2265,7 @@ __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); @@ -2268,7 +2282,6 @@ void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, /** * @} */ -#endif /* SPI_I2S_SUPPORT */ #endif /* defined (SPI1) || defined (SPI3) */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/LICENSE.md b/system/Drivers/STM32WL3x_HAL_Driver/LICENSE.md index eb0b33cda6..85878f41ac 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/LICENSE.md +++ b/system/Drivers/STM32WL3x_HAL_Driver/LICENSE.md @@ -24,4 +24,4 @@ ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/system/Drivers/STM32WL3x_HAL_Driver/README.md b/system/Drivers/STM32WL3x_HAL_Driver/README.md index 7880768d7a..5fceb06f61 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/README.md +++ b/system/Drivers/STM32WL3x_HAL_Driver/README.md @@ -1,6 +1,6 @@ # STM32CubeWL3 HAL Driver MCU Component -![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32wl3x-hal-driver.svg?color=brightgreen) +![tag](https://img.shields.io/badge/tag-v1.5.0-brightgreen.svg) ## Overview @@ -33,4 +33,4 @@ The full **STM32CubeWL3** MCU package is available [here](https://github.com/STM ## Troubleshooting -Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. \ No newline at end of file diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Release_Notes.html b/system/Drivers/STM32WL3x_HAL_Driver/Release_Notes.html index fccf365508..f24e1df16c 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32WL3x_HAL_Driver/Release_Notes.html @@ -25,7 +25,7 @@ } .display.math{display: block; text-align: center; margin: 0.5rem auto;} - + @@ -34,7 +34,7 @@

Release Notes for

STM32WL3xx HAL Drivers

-

Copyright © 2024-2025 STMicroelectronics

+

Copyright © 2024-2026 STMicroelectronics

@@ -68,26 +68,81 @@

Purpose

Update History

- - + +

Main Changes

    -
  • Correction to the I2C HAL driver
    • +
  • Updated the MRSUBG HAL driver to enhance support for 169MHz +transmission and reception on suitable boards.
    • +
  • Updated the MRSUBG LL driver to work-around a radio PLL startup +issue.
    • +
  • Updated the MRSUBG channel filter bandwidth table (increased +configurability).
    • +
  • Added several PWR LL APIs to manipulate CR2 register fields.

Contents

HAL Drivers updates

    -
  • HAL I2C driver +
  • HAL MRSUBG/ LL MRSUBG driver
      -
    • Pin definitions for SMBUS and Fast Mode Plus now split across the -two I2C IP instances (I2C1 and I2C2).
      • +

    • Added 169MHz TX and RX preparation functions

      +
      void HAL_MRSubG_169MHz_prepareTx(void)
      +
      • +
      void HAL_MRSubG_169MHz_prepareRx(void)
      + +

    • s_Channel_Filter_Bandwidth[] has been extended +with more configuration values (160 vs 99)

      +

      Note: legacy values have been kept

      • +

    • AFC1_CONFIG register set to 0x18 (reset value) in +HAL_MRSubG_Init()

      • +

    • LL_MRSubG_StrobeCommand(MRSubGCmd xCommandCode) +updated to implement a SW work-around for the “Incorrect base frequency +at PLL startup” issue (Refer to the product Errata documents for more +details).

      • +
    • +
  • HAL PWR/ LL PWR driver +
      +
    • Added following LL APIs to read & set additional CR2 register +fields +
      __STATIC_INLINE void LL_PWR_EnableRFREGEN(void)
      +
      • +
      __STATIC_INLINE void LL_PWR_DisableRFREGEN(void)
      + +
      __STATIC_INLINE uint32_t LL_PWR_GetRFREGEN(void)
      + +
      __STATIC_INLINE void LL_PWR_EnableRFREGBYP(void)
      + +
      __STATIC_INLINE void LL_PWR_DisableRFREGBYP(void)
      + +
      __STATIC_INLINE uint32_t LL_PWR_GetRFREGBYP(void)
      + +
      __STATIC_INLINE void LL_PWR_EnableRFREGCEXT(void)
      + +
      __STATIC_INLINE void LL_PWR_DisableRFREGCEXT(void)
      + +
      __STATIC_INLINE uint32_t LL_PWR_GetRFREGCEXT(void)
      + +
      __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_RFREGON_STATUS(void)
      + +
      __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_RFREGRDY(void)
      + +
      __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_LPREG_VH_STATUS(void)
      + +
      __STATIC_INLINE void LL_PWR_EnableLPREGVH(void)
      + +
      __STATIC_INLINE void LL_PWR_DisableLPREGVH(void)
      + +
      __STATIC_INLINE uint32_t LL_PWR_GetLPREGVH(void)
      + +
    • Removed LL functions related to non-user registers (not used by any +code)

Backward compatibility

    -
  • Not applicable
    • +
  • Yes

Known Limitations

    @@ -104,18 +159,115 @@

    Notes

+ + +
+

Main Changes

+
    +
  • Update of I2C and SMBUS HAL drivers to fix build warnings.
    • +
  • Added LL APIs to manipulate AGC_ANA_ENG and PA_REG bitfields.
    • +
  • Added LL APIs related to RCC “CR” register
    • +
  • fixed HAL_RCCEx_GetPeriphCLKFreq()
    • +
+

Contents

+

HAL Drivers updates

+
    +
  • HAL I2C driver +
      +
    • Reworked ‘Fast Mode Plus’ macro definition.
      • +
    • +
  • HAL SMBUS driver +
      +
    • Reworked ‘Fast Mode Plus’ macro definition.
      • +
    • +
  • HAL MRSUBG/ LL MRSUBG driver +
      +
    • Fixed a typo in a bitmask macro (“nAND” -> “NAND”), to align to +its CMSIS definition
      • +
    • Added get & set LL APIs for PA_REG fields
      • +
    • Added LL APIs for AGC_ANA_ENG register fields
      • +
    • +
  • HAL RCC/ LL RCC driver +
      +
    • added get & set LL APIs for CR register bit #15 (“FMRAT”) +
      __STATIC_INLINE void LL_RCC_FMRAT_UseHSI(void)
      +
      • +
      __STATIC_INLINE void LL_RCC_FMRAT_UseHSE(void)
      + +
      __STATIC_INLINE uint32_t LL_RCC_FMRAT_IsHSI(void)
      + +
    • HAL_RCCEx_GetPeriphCLKFreq() fixed to return correct value for all +clock configurations
      • +
    • +
+

Backward compatibility

+
    +
  • Yes
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Dependencies

+
    +
  • None
    • +
+

Notes

+
    +
  • None
    • +
+
+
+
+ + +
+

Main Changes

+
    +
  • Correction to the I2C and SMBUS HAL drivers
    • +
+

Contents

+

HAL Drivers updates

+
    +
  • HAL I2C driver +
      +
    • Pin definitions for SMBUS and Fast Mode Plus now split across the +two I2C IP instances (I2C1 and I2C2).
      • +
    • +
+

Backward compatibility

+
    +
  • Not applicable
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Dependencies

+
    +
  • None
    • +
+

Notes

+
    +
  • None
    • +
+
+
+
-

Main Changes

+

Main Changes

  • HAL and LL drivers updates to support STM32WL3Rx product line.
  • Corrections/enhancements to the following HAL drivers: ADC, MRSUBG, RCC, MRSUBG Timer, GPIO, UART, USART, LCSC, PWR.
-

Contents

-

HAL Drivers updates

+

Contents

+

HAL Drivers updates

  • HAL ADC driver
      @@ -184,19 +336,19 @@

      Supported Devices and boards

    • NUCLEO-WL3RKB1 board
    • NUCLEO-WL3RKB2 board
    -

    Backward compatibility

    +

    Backward compatibility

    • Not applicable
    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Dependencies

    +

    Dependencies

    • None
    -

    Notes

    +

    Notes

    • None
    @@ -207,12 +359,12 @@

    Notes

    -

    Main Changes

    +

    Main Changes

    Release of HAL and LL drivers for STM32WL3x devices

    -

    Contents

    -

    HAL Drivers updates

    +

    Contents

    +

    HAL Drivers updates

    • HAL MRSUBG driver
        @@ -259,19 +411,19 @@

        Supported Devices and
      • NUCLEO-WL33CC1 board
      • NUCLEO-WL33CC2 board

      -

      Backward compatibility

      +

      Backward compatibility

      • Not applicable
      -

      Known Limitations

      +

      Known Limitations

      • None
      -

      Dependencies

      +

      Dependencies

      • None
      -

      Notes

      +

      Notes

      • None
      @@ -282,7 +434,7 @@

      Notes

      -

      Main Changes

      +

      Main Changes

      Release of HAL and LL drivers for STM32WL3x devices

      @@ -345,7 +497,7 @@

      Release

Check the code documentation for further details.

-

Contents

+

Contents

  • Release of HAL/LL drivers
      @@ -362,19 +514,19 @@

      Supported Devices and
    • NUCLEO-WL33CC1 board
    • NUCLEO-WL33CC2 board

    -

    Backward compatibility

    +

    Backward compatibility

    • Not applicable
    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Dependencies

    +

    Dependencies

    • None
    -

    Notes

    +

    Notes

    • None
    @@ -385,12 +537,12 @@

    Notes

    -

    Main Changes

    +

    Main Changes

    First Official Release of HAL and LL drivers for STM32WL33 devices

    -

    Contents

    +

    Contents

    • First Official Release of HAL/LL drivers
        @@ -406,19 +558,19 @@

        Supported Devices and
        • NUCLEO-WL33CC board
        -

        Backward compatibility

        +

        Backward compatibility

        • Not applicable
        -

        Known Limitations

        +

        Known Limitations

        • None
        -

        Dependencies

        +

        Dependencies

        • None
        -

        Notes

        +

        Notes

        • None
        diff --git a/system/Drivers/STM32WL3x_HAL_Driver/SW_Security_Level.md b/system/Drivers/STM32WL3x_HAL_Driver/SW_Security_Level.md new file mode 100644 index 0000000000..0d15220b09 --- /dev/null +++ b/system/Drivers/STM32WL3x_HAL_Driver/SW_Security_Level.md @@ -0,0 +1,47 @@ + + +## Copyright (c) 2026 STMicroelectronics. +## All rights reserved +
        +
        + +## SW Security Classification + +[STM32Trust software security policies](https://wiki.st.com/stm32mcu/wiki/Security:STM32Trust_software_security_policies) define four levels of SW Security classification, each level defines a set of security policies for the applicable SW. + +| SW | SW Security Level +|:--------- |:-------| +| **STM32WL3x HAL Driver** | Medium| + + +
        + +## IMPORTANT SECURITY NOTICE + +The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that: + +- ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified. + +- Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product. + +- Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies. + +- While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application. + +- All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. + +AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise. + +
        + +## IMPORTANT NOTICE - READ CAREFULLY + +STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgment. + +Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers' products. +No license, express or implied, to any intellectual property right is granted by ST herein. +Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. +ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. +Information in this document supersedes and replaces information previously supplied in any prior versions of this document. + +Copyright (c) 2026 STMicroelectronics - All rights reserved \ No newline at end of file diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_adc.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_adc.c index 0f339542cf..8138a85a61 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_adc.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_adc.c @@ -1030,7 +1030,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti * ADC_IRQ_FLAG_AWD1 ADC analog watchdog event * ADC_IRQ_FLAG_EOS ADC sequence of conversion completed event * ADC_IRQ_FLAG_EODS ADC Down Sampler conversion completed Event - * (1) todo: Only available on STM32WB0x + * (1) todo: Only available on STM32WL3x * @param Timeout Timeout value in millisecond. * @note The relevant flag is cleared if found to be set, except for * ADC_IRQ_FLAG_OVRDS. diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash.c index d2060df3e4..95fe105797 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash.c @@ -142,7 +142,7 @@ static void FLASH_Program_Burst(uint32_t Address, uint32_t DataAddress) */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); @@ -202,7 +202,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint */ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c index d1b9f3dd01..bd2f5a4cb8 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c @@ -107,7 +107,7 @@ static void FLASH_Program_OTPWord(uint32_t Address, uint32_t Data); */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status = HAL_OK; uint32_t index; /* Check the parameters */ @@ -221,7 +221,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) */ HAL_StatusTypeDef HAL_FLASHEx_OTPWrite(uint32_t Address, uint32_t Data) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_ADDR_ALIGNED_32BITS(Address)); diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_gpio.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_gpio.c index 494d58a355..c1f16cee8f 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_gpio.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_gpio.c @@ -132,7 +132,7 @@ /** @addtogroup GPIO_Private_Constants GPIO Private Constants * @{ */ -#define GPIO_NUMBER (16u) +#define GPIO_NUMBER (16U) /** * @} */ @@ -167,7 +167,7 @@ */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - uint32_t position = 0x00u; + uint32_t position = 0x00U; uint32_t iocurrent; uint32_t temp; @@ -178,12 +178,12 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ - while (((GPIO_Init->Pin) >> position) != 0x00u) + while (((GPIO_Init->Pin) >> position) != 0x00U) { /* Get current io position */ - iocurrent = (GPIO_Init->Pin) & (1uL << position); + iocurrent = (GPIO_Init->Pin) & (1UL << position); - if (iocurrent != 0x00u) + if (iocurrent != 0x00U) { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ @@ -193,8 +193,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); - temp |= (GPIO_Init->Speed << (position * 2u)); + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + temp |= (GPIO_Init->Speed << (position * 2U)); GPIOx->OSPEEDR = temp; /* Configure the IO Output Type */ @@ -227,25 +227,25 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3u]; - temp &= ~(0xFu << ((position & 0x07u) * 4u)); - temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); - GPIOx->AFR[position >> 3u] = temp; + temp = GPIOx->AFR[position >> 3U]; + temp &= ~(0xFUL << ((position & 0x07U) * 4U)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + GPIOx->AFR[position >> 3U] = temp; } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); GPIOx->MODER = temp; /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ - if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) { /* Edge/Level line configuration */ - if ((GPIO_Init->Mode & DETECTION_TYPE) != 0x00u) + if ((GPIO_Init->Mode & DETECTION_TYPE) != 0x00U) { temp = SYSCFG->IO_DTR; if (GPIOx == GPIOA) @@ -262,7 +262,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) } /* Edge selection configuration */ - if ((GPIO_Init->Mode & EDGE_SELECTION) != 0x00u) + if ((GPIO_Init->Mode & EDGE_SELECTION) != 0x00U) { temp = SYSCFG->IO_IBER; @@ -280,7 +280,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) } /* Trigger mode configuration */ - if ((GPIO_Init->Mode & TRIGGER_MODE) != 0x00u) + if ((GPIO_Init->Mode & TRIGGER_MODE) != 0x00U) { temp = SYSCFG->IO_IEVR; @@ -330,7 +330,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { - uint32_t position = 0x00u; + uint32_t position = 0x00U; uint32_t iocurrent; uint32_t tmp; @@ -339,12 +339,12 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Configure the port pins */ - while ((GPIO_Pin >> position) != 0x00u) + while ((GPIO_Pin >> position) != 0x00U) { /* Get current io position */ - iocurrent = (GPIO_Pin) & (1uL << position); + iocurrent = (GPIO_Pin) & (1UL << position); - if (iocurrent != 0x00u) + if (iocurrent != 0x00U) { /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ @@ -398,19 +398,19 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO in Analog Mode */ - GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u)); + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U)); /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ; + GPIOx->AFR[position >> 3U] &= ~(0xFUL << ((position & 0x07U) * 4U)) ; /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); } position++; @@ -447,7 +447,7 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); - if ((GPIOx->IDR & GPIO_Pin) != 0x00u) + if ((GPIOx->IDR & GPIO_Pin) != 0x00U) { bitstatus = GPIO_PIN_SET; } @@ -517,7 +517,7 @@ void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint /** * @brief Toggle the specified GPIO pin. - * @param GPIOx where x can be (A..B) to select the GPIO peripheral for STM32WB0x family + * @param GPIOx where x can be (A..B) to select the GPIO peripheral for STM32WL3x family * @param GPIO_Pin specifies the pin to be toggled. * @retval None */ @@ -566,7 +566,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) tmp = GPIOx->LCKR; /* read again in order to confirm lock is active */ - if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U) { return HAL_OK; } @@ -585,7 +585,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) void HAL_GPIO_EXTI_IRQHandler(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { /* EXTI line interrupt detected */ - if (__HAL_GPIO_EXTI_GET_IT(GPIOx, GPIO_Pin) != 0x00u) + if (__HAL_GPIO_EXTI_GET_IT(GPIOx, GPIO_Pin) != 0x00U) { __HAL_GPIO_EXTI_CLEAR_IT(GPIOx, GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIOx, GPIO_Pin); diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_i2s.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_i2s.c index 6c66a13071..6113d3229c 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_i2s.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_i2s.c @@ -185,7 +185,6 @@ #ifdef HAL_I2S_MODULE_ENABLED -#if defined(SPI_I2S_SUPPORT) /** @addtogroup STM32WL3x_HAL_Driver * @{ */ @@ -1602,7 +1601,7 @@ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) * the configuration information for I2S module * @retval HAL state */ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) +HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s) { return hi2s->State; } @@ -1613,7 +1612,7 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) * the configuration information for I2S module * @retval I2S Error Code */ -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) +uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s) { return hi2s->ErrorCode; } @@ -1848,6 +1847,5 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, /** * @} */ -#endif /* SPI_I2S_SUPPORT */ #endif /* HAL_I2S_MODULE_ENABLED */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_mrsubg.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_mrsubg.c index 256ce45b53..8dc814fd98 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_mrsubg.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_mrsubg.c @@ -34,6 +34,13 @@ * @{ */ #define MAX_DBM 0x51 +#define MRSUBG_CHFLT_M_VALUES 16U +#define MRSUBG_CHFLT_E_VALUES 10U +#define MRSUBG_CHFLT_TABLE_SIZE (MRSUBG_CHFLT_M_VALUES * MRSUBG_CHFLT_E_VALUES) +#if defined(IS_169MHZ) +#define MRSUBG_169MHZ_IF_GRANULARITY 244U +#define MRSUBG_169MHZ_FDEV_MULTIPLIER 5U +#endif /* IS_169MHZ */ /** * @} @@ -85,18 +92,22 @@ * @{ */ -static const uint32_t s_Channel_Filter_Bandwidth[99] = +static const uint32_t s_Channel_Filter_Bandwidth[MRSUBG_CHFLT_TABLE_SIZE] = { - 1600000, 1510000, 1422000, 1332000, 1244000, 1154000, 1066000, \ - 976000, 888000, 800000, 755000, 711000, 666000, 622000, 577000, \ - 533000, 488000, 444000, 400000, 377000, 355000, 333000, 311000, \ - 288000, 266000, 244000, 222000, 200000, 188000, 178000, 166000, \ - 155000, 144000, 133000, 122000, 111000, 100000, 94400, 88900, 83300, \ - 77800, 72200, 66700, 61100, 55600, 50000, 47200, 44400, 41600, 38900, \ - 36100, 33300, 30500, 27800, 25000, 23600, 22200, 20800, 19400, 18100, \ - 16600, 15300, 13900, 12500, 11800, 11100, 10400, 9700, 9000, 8300, 7600, \ - 6900, 6125, 5910, 5550, 5200, 4870, 4500, 4100, 3800, 3500, 3125, 2940, \ - 2780, 2600, 2400, 2200, 2100, 1900, 1700 + 1600000, 1510000, 1422000, 1332000, 1244000, 1154000, 1066000, 976000, \ + 888000, 800000, 755600, 711100, 666700, 622200, 577800, 533300, \ + 800000, 755000, 711000, 666000, 622000, 577000, 533000, 488000, \ + 444000, 400000, 377800, 355600, 333300, 311100, 288900, 266700, \ + 400000, 377000, 355000, 333000, 311000, 288000, 266000, 244000, \ + 222000, 200000, 188900, 177800, 166700, 155600, 144400, 133300, \ + 200000, 188000, 178000, 166000, 155000, 144000, 133000, 122000, \ + 111000, 100000, 94400, 88900, 83300, 77800, 72200, 66700, \ + 100000, 94400, 88900, 83300, 77800, 72200, 66700, 61100, 55600, 50000, 47200, 44400, 41700, 38900, 36100, 33300, \ + 50000, 47200, 44400, 41600, 38900, 36100, 33300, 30500, 27800, 25000, 23600, 22200, 20800, 19400, 18060, 16670, \ + 25000, 23600, 22200, 20800, 19400, 18100, 16600, 15300, 13900, 12500, 11800, 11100, 10420, 9720, 9030, 8330, \ + 12500, 11800, 11100, 10400, 9700, 9000, 8300, 7600, 6900, 6250, 5900, 5560, 5210, 4860, 4510, 4170, \ + 6125, 5910, 5550, 5200, 4870, 4500, 4100, 3800, 3500, 3120, 2950, 2780, 2600, 2430, 2260, 2080, \ + 3125, 2940, 2780, 2600, 2400, 2200, 2100, 1900, 1700, 1560, 1480, 1390, 1300, 1220, 1130, 1040 }; const uint32_t SFD_2FSK[] = @@ -112,6 +123,12 @@ const uint32_t SFD_4FSK[] = }; static WMbusSubmode s_cWMbusSubmode = WMBUS_SUBMODE_NOT_CONFIGURED; +#if defined(IS_169MHZ) +static uint32_t s_mrsubg_169_default_base_freq = 0U; +static uint32_t s_mrsubg_169_default_fdev = 0U; +static uint32_t s_mrsubg_169_rx_base_backup = 0U; +static uint32_t s_mrsubg_169_tx_fdev_backup = 0U; +#endif /* IS_169MHZ */ /** * @} @@ -130,6 +147,13 @@ static void MRSubG_ComputeSynthWord(uint32_t frequency, uint8_t *synth_int, uint static int32_t MRSubG_ConvertRssiToDbm(uint16_t rssi_level_from_register); static uint8_t MRSubG_GetAllowedMaxOutputPower(MRSubG_PA_DRVMode paMode); static void MRSUBG_EvaluateDSSS(MRSubGModSelect xModulation, uint8_t dsssExponent); +#if defined(IS_169MHZ) +static void MRSubG_169MHz_CaptureDefaults(void); +static void MRSubG_169MHz_RestoreBaseFrequency(void); +static void MRSubG_169MHz_AdjustBaseFrequencyForRx(void); +static void MRSubG_169MHz_AdjustFrequencyDevForTx(void); +static void MRSubG_169MHz_RestoreFrequencyDev(void); +#endif /* IS_169MHZ */ /** * @brief Computes the synth word from a given frequency. @@ -237,13 +261,17 @@ static void MRSubG_SearchDatarateME(uint32_t lDatarate, uint16_t *pcM, uint8_t * static uint32_t MRSubG_ComputeFreqDeviation(uint8_t cM, uint8_t cE, uint8_t bs) { uint32_t f_xo = LL_GetXTALFreq(); + uint64_t denominator = ((uint64_t)bs) * (1ULL << 19); + uint64_t mantissa; if (cE == 0) { - return (uint32_t)((uint64_t)f_xo * (cM * bs / 8) / (bs * (1 << 19))); + mantissa = (((uint64_t)cM) * ((uint64_t)bs)) / 8ULL; + return (uint32_t)(((uint64_t)f_xo * mantissa) / denominator); } - return (uint32_t)((uint64_t)f_xo * ((256 + cM) * (1 << (cE - 1)) * bs / 8) / (bs * (1 << 19)));; + mantissa = ((((uint64_t)256 + (uint64_t)cM) * (1ULL << (cE - 1)) * (uint64_t)bs) / 8ULL); + return (uint32_t)(((uint64_t)f_xo * mantissa) / denominator); } /** @@ -297,15 +325,15 @@ static void MRSubG_SearchFreqDevME(uint32_t lFDev, uint8_t *pcM, uint8_t *pcE, u * The API will search the closer value according to a fixed table of channel * bandwidth values (@ref s_Channel_Filter_Bandwidth) returning the corresponding mantissa * and exponent value. - * @param lBandwidth bandwidth expressed in Hz. This parameter ranging between 1700 and 1600000. + * @param lBandwidth bandwidth expressed in Hz. This parameter ranging between 1040 and 1600000. * @param pcM pointer to the returned mantissa value. * @param pcE pointer to the returned exponent value. * @retval None. */ static void MRSubG_SearchChannelBwME(uint32_t lBandwidth, uint8_t *pcM, uint8_t *pcE) { - int8_t i; - int8_t i_tmp; + int16_t i; + int16_t i_tmp; uint32_t f_dig; int32_t chfltCalculation[3]; uint8_t j; @@ -314,7 +342,7 @@ static void MRSubG_SearchChannelBwME(uint32_t lBandwidth, uint8_t *pcM, uint8_t f_dig = LL_GetXTALFreq() / 3; /* Search the channel filter bandwidth table index */ - for (i = 0; i < 99 && + for (i = 0; i < MRSUBG_CHFLT_TABLE_SIZE && (lBandwidth < (uint32_t)(((uint64_t)s_Channel_Filter_Bandwidth[i] * f_dig) / 16000000)); i++) ; @@ -326,7 +354,7 @@ static void MRSubG_SearchChannelBwME(uint32_t lBandwidth, uint8_t *pcM, uint8_t for (j = 0; j < 3; j++) { - if (((i_tmp + j - 1) >= 0) && ((i_tmp + j - 1) <= 98)) + if (((i_tmp + j - 1) >= 0) && ((i_tmp + j - 1) < MRSUBG_CHFLT_TABLE_SIZE)) { chfltCalculation[j] = (int32_t)lBandwidth - (int32_t)(((uint64_t)s_Channel_Filter_Bandwidth[i_tmp + j - 1] * f_dig) / 16000000); @@ -349,8 +377,8 @@ static void MRSubG_SearchChannelBwME(uint32_t lBandwidth, uint8_t *pcM, uint8_t } } - (*pcE) = (uint8_t)(i / 9); - (*pcM) = (uint8_t)(i % 9); + (*pcE) = (uint8_t)(i / MRSUBG_CHFLT_M_VALUES); + (*pcM) = (uint8_t)(i % MRSUBG_CHFLT_M_VALUES); } /* @@ -415,6 +443,66 @@ static void MRSUBG_EvaluateDSSS(MRSubGModSelect xModulation, uint8_t dsssExponen MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->DSSS_CTRL, MR_SUBG_GLOB_STATIC_DSSS_CTRL_SPREADING_EXP, dsssExponent); MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->DSSS_CTRL, MR_SUBG_GLOB_STATIC_DSSS_CTRL_ACQ_THR, dsss_acq_thr); } +#if defined(IS_169MHZ) + +static void MRSubG_169MHz_CaptureDefaults(void) +{ + if (s_mrsubg_169_default_base_freq == 0U) + { + s_mrsubg_169_default_base_freq = HAL_MRSubG_GetFrequencyBase(); + } + + if (s_mrsubg_169_default_fdev == 0U) + { + s_mrsubg_169_default_fdev = HAL_MRSubG_GetFrequencyDev(); + } +} + +static void MRSubG_169MHz_RestoreBaseFrequency(void) +{ + MRSubG_169MHz_CaptureDefaults(); + HAL_MRSubG_SetFrequencyBase(s_mrsubg_169_default_base_freq); + s_mrsubg_169_rx_base_backup = 0U; +} + +static void MRSubG_169MHz_AdjustBaseFrequencyForRx(void) +{ + MRSubG_169MHz_CaptureDefaults(); + + if (s_mrsubg_169_rx_base_backup == 0U) + { + uint32_t if_dig = __HAL_MRSUBG_GET_IF_OFFSET_DIG() * MRSUBG_169MHZ_IF_GRANULARITY; + s_mrsubg_169_rx_base_backup = HAL_MRSubG_GetFrequencyBase(); + HAL_MRSubG_SetFrequencyBase(s_mrsubg_169_rx_base_backup - if_dig); + } +} + +static void MRSubG_169MHz_AdjustFrequencyDevForTx(void) +{ + MRSubG_169MHz_CaptureDefaults(); + + if (s_mrsubg_169_tx_fdev_backup == 0U) + { + s_mrsubg_169_tx_fdev_backup = HAL_MRSubG_GetFrequencyDev(); + HAL_MRSubG_SetFrequencyDev(s_mrsubg_169_tx_fdev_backup * MRSUBG_169MHZ_FDEV_MULTIPLIER); + } +} + +static void MRSubG_169MHz_RestoreFrequencyDev(void) +{ + MRSubG_169MHz_CaptureDefaults(); + + if (s_mrsubg_169_tx_fdev_backup != 0U) + { + HAL_MRSubG_SetFrequencyDev(s_mrsubg_169_tx_fdev_backup); + s_mrsubg_169_tx_fdev_backup = 0U; + } + else + { + HAL_MRSubG_SetFrequencyDev(s_mrsubg_169_default_fdev); + } +} +#endif /* IS_169MHZ */ /** * @} @@ -455,7 +543,7 @@ uint8_t HAL_MRSubG_Init(SMRSubGConfig_t *pxSRadioInitStruct) HAL_MRSubG_MspInit(); /* Setup design values for default registers */ - MODIFY_REG_FIELD(MR_SUBG_RADIO->AFC1_CONFIG, MR_SUBG_RADIO_AFC1_CONFIG_AFC_FAST_PERIOD, 0x00); + MODIFY_REG_FIELD(MR_SUBG_RADIO->AFC1_CONFIG, MR_SUBG_RADIO_AFC1_CONFIG_AFC_FAST_PERIOD, 0x18); MODIFY_REG_FIELD(MR_SUBG_RADIO->CLKREC_CTRL0, MR_SUBG_RADIO_CLKREC_CTRL0_PSTFLT_LEN, 0x01); MODIFY_REG_FIELD(MR_SUBG_RADIO->CLKREC_CTRL0, MR_SUBG_RADIO_CLKREC_CTRL0_CLKREC_P_GAIN_FAST, 0x03); @@ -531,20 +619,20 @@ void HAL_MRSubG_SetFrequencyBase(uint32_t lFBase) MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_SYNTH_FRAC, synth_frac); MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->ADDITIONAL_CTRL, MR_SUBG_GLOB_DYNAMIC_ADDITIONAL_CTRL_CH_NUM, 0x00); -#if defined(STM32WL33XA) + b_factor = (band / 4) - 1; + +#if defined(IS_169MHZ) + /* 169 MHz profile-specific BS encoding. */ b_factor = (20 - band) / 12; -#elif defined(STM32WL3RX) +#endif /* IS_169MHZ */ + +#if defined(STM32WL3RX) + /* STM32WL3RX-specific DIV12 handling for the LOW_LOW band. */ if (band == 12) { SET_BIT(MR_SUBG_RADIO->RFANA_PLL_IN, MR_SUBG_RADIO_RFANA_PLL_IN_DIV12_SEL); b_factor = 1; } - else - { - b_factor = (band / 4) - 1; - } -#else - b_factor = (band / 4) - 1; #endif /* STM32WL3RX */ MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS, b_factor); @@ -556,24 +644,21 @@ void HAL_MRSubG_SetFrequencyBase(uint32_t lFBase) */ uint32_t HAL_MRSubG_GetFrequencyBase(void) { -#if defined(STM32WL33XA) - uint8_t bs = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS); + uint8_t bs = (READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS) + 1) * 4; + +#if defined(IS_169MHZ) + /* 169 MHz profile-specific BS decoding. */ + bs = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS); bs = bs ? 8 : 20; -#else - uint8_t bs; +#endif /* IS_169MHZ */ + #if defined(STM32WL3RX) + /* STM32WL3RX-specific DIV12 handling for the LOW_LOW band. */ if (READ_BIT(MR_SUBG_RADIO->RFANA_PLL_IN, MR_SUBG_RADIO_RFANA_PLL_IN_DIV12_SEL)) { bs = 12; } - else - { - bs = (READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS) + 1) * 4; - } -#else - bs = (READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS) + 1) * 4; #endif /* STM32WL3RX */ -#endif /* STM32WL33XA */ uint8_t synth_int = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_SYNTH_INT); uint32_t synth_frac = READ_REG(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ) & MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_SYNTH_FRAC; @@ -643,23 +728,21 @@ void HAL_MRSubG_SetFrequencyDev(uint32_t lFDev) uint8_t uFDevE; uint8_t bs; -#if defined(STM32WL33XA) + bs = (READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS) + 1) * 4; + +#if defined(IS_169MHZ) + /* 169 MHz profile-specific BS decoding. */ bs = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS); bs = bs ? 8 : 20; -#else +#endif /* IS_169MHZ */ + #if defined(STM32WL3RX) + /* STM32WL3RX-specific DIV12 handling for the LOW_LOW band. */ if (READ_BIT(MR_SUBG_RADIO->RFANA_PLL_IN, MR_SUBG_RADIO_RFANA_PLL_IN_DIV12_SEL)) /* Checking if 315MHz band */ { bs = 12; } - else - { - bs = (READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS) + 1) * 4; - } -#else - bs = (READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS) + 1) * 4; #endif /* STM32WL3RX */ -#endif /* STM32WL33XA */ /* Calculates the frequency deviation mantissa and exponent */ MRSubG_SearchFreqDevME(lFDev, &uFDevM, &uFDevE, bs); @@ -681,23 +764,21 @@ uint32_t HAL_MRSubG_GetFrequencyDev(void) uint32_t factor2; uint8_t bs; -#if defined(STM32WL33XA) + bs = (READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS) + 1) * 4; + +#if defined(IS_169MHZ) + /* 169 MHz profile-specific BS decoding. */ bs = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS); bs = bs ? 8 : 20; -#else +#endif /* IS_169MHZ */ + #if defined(STM32WL3RX) + /* STM32WL3RX-specific DIV12 handling for the LOW_LOW band. */ if (READ_BIT(MR_SUBG_RADIO->RFANA_PLL_IN, MR_SUBG_RADIO_RFANA_PLL_IN_DIV12_SEL)) /* Checking if 315MHz band */ { bs = 12; } - else - { - bs = (READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS) + 1) * 4; - } -#else - bs = (READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS) + 1) * 4; #endif /* STM32WL3RX */ -#endif /* STM32WL33XA */ fdev_m = READ_REG(MR_SUBG_GLOB_DYNAMIC->MOD1_CONFIG) & MR_SUBG_GLOB_DYNAMIC_MOD1_CONFIG_FDEV_M; fdev_e = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD1_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD1_CONFIG_FDEV_E); @@ -709,6 +790,32 @@ uint32_t HAL_MRSubG_GetFrequencyDev(void) return f_dev; } +#if defined(IS_169MHZ) + +/** + * @brief Prepare the radio configuration for 169 MHz TX operations. + * Restores the base frequency to the default configuration and + * adjusts the frequency deviation for 169 MHz transmission. + * @retval None. + */ +void HAL_MRSubG_169MHz_prepareTx(void) +{ + MRSubG_169MHz_RestoreBaseFrequency(); + MRSubG_169MHz_AdjustFrequencyDevForTx(); +} + +/** + * @brief Prepare the radio configuration for 169 MHz RX operations. + * Restores the frequency deviation to the default configuration and + * adjusts the base frequency for 169 MHz reception. + * @retval None. + */ +void HAL_MRSubG_169MHz_prepareRx(void) +{ + MRSubG_169MHz_RestoreFrequencyDev(); + MRSubG_169MHz_AdjustBaseFrequencyForRx(); +} +#endif /* IS_169MHZ */ /** * @brief Set the channel filter bandwidth. @@ -753,23 +860,24 @@ void HAL_MRSubG_SetChannelBW(uint32_t lBandwidth) if_offset = (((f_if * 100) * 65536) / f_dig) * 10; /* Set IF */ -#if defined(STM32WL33XA) - /* WL33xA */ +#if defined(IS_169MHZ) + /* 169 MHz profile-specific IF analog offset handling. */ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->IF_CTRL, MR_SUBG_GLOB_STATIC_IF_CTRL_IF_OFFSET_ANA, 0); -#elif defined(STM32WL3RX) - /* Checking if 315MHz band */ +#endif /* IS_169MHZ */ + +#if !defined(IS_169MHZ) && defined(STM32WL3RX) + /* STM32WL3RX-specific IF analog offset handling for the LOW_LOW band. */ if (READ_BIT(MR_SUBG_RADIO->RFANA_PLL_IN, MR_SUBG_RADIO_RFANA_PLL_IN_DIV12_SEL)) { - uint32_t if_offset_ana = if_offset * 3 / 2; - MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->IF_CTRL, MR_SUBG_GLOB_STATIC_IF_CTRL_IF_OFFSET_ANA, if_offset_ana); + MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->IF_CTRL, MR_SUBG_GLOB_STATIC_IF_CTRL_IF_OFFSET_ANA, (if_offset * 3 / 2)); } else { MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->IF_CTRL, MR_SUBG_GLOB_STATIC_IF_CTRL_IF_OFFSET_ANA, if_offset); } -#else +#elif !defined(IS_169MHZ) MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->IF_CTRL, MR_SUBG_GLOB_STATIC_IF_CTRL_IF_OFFSET_ANA, if_offset); -#endif /*STM32WL3RX*/ +#endif /* !defined(IS_169MHZ) && defined(STM32WL3RX) */ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->IF_CTRL, MR_SUBG_GLOB_STATIC_IF_CTRL_IF_OFFSET_DIG, if_offset); } @@ -784,17 +892,19 @@ uint32_t HAL_MRSubG_GetChannelBW(void) uint8_t ce; uint8_t index; uint32_t fclk; - uint32_t correction_factor; fclk = LL_GetXTALFreq() / 3; - correction_factor = fclk / 16000000; cm = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD1_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD1_CONFIG_CHFLT_M); ce = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD1_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD1_CONFIG_CHFLT_E); - index = ce * 9 + cm; + if (ce > MRSUBG_CHFLT_E_VALUES - 1) + { + ce = MRSUBG_CHFLT_E_VALUES - 1; + } - return correction_factor * s_Channel_Filter_Bandwidth[index]; + index = (ce * MRSUBG_CHFLT_M_VALUES) + cm; + return (uint32_t)(((uint64_t)s_Channel_Filter_Bandwidth[index] * fclk) / 16000000); } /** @@ -1190,7 +1300,7 @@ void HAL_MRSubG_PacketBasicInit(MRSubG_PcktBasicFields_t *pxPktBasicInit) LL_MRSubG_PacketHandlerWhitening(pxPktBasicInit->DataWhitening); LL_MRSubG_PacketHandlerCoding(pxPktBasicInit->Coding); LL_MRSubG_PacketHandlerSetCrcMode(pxPktBasicInit->CrcMode); - MODIFY_REG(MR_SUBG_GLOB_STATIC->CRC_INIT, MR_SUBG_GLOB_STATIC_CRC_INIT_CRC_INIT_VAL, 0xFFFFFFFF); + WRITE_REG(MR_SUBG_GLOB_STATIC->CRC_INIT, 0xFFFFFFFF); /* Set the Fixed or Variable Packet Length mode */ LL_MRSUBG_SetFixedVariableLength(pxPktBasicInit->FixVarLength); diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_mrsubg_timer.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_mrsubg_timer.c index a2fecfa846..fc61c66d24 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_mrsubg_timer.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_mrsubg_timer.c @@ -498,7 +498,7 @@ uint32_t HAL_MRSUBG_TIMER_StartVirtualTimer(VTIMER_HandleType_t *timerHandle, ui */ uint32_t HAL_MRSUBG_TIMER_StartVirtualTimerMs(VTIMER_HandleType_t *timerHandle, uint32_t msRelTimeout) { - uint64_t time = msRelTimeout * 1000; + uint64_t time = (uint64_t)msRelTimeout * 1000U; uint8_t retVal; retVal = _start_timer(timerHandle, (HAL_MRSUBG_TIMER_GetCurrentSysTime() + time)); _virtualTimeBaseEnable(ENABLE); diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_rcc_ex.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_rcc_ex.c index d509d251ec..d7fd7d43df 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_rcc_ex.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_rcc_ex.c @@ -264,10 +264,26 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_LPUART1_CLKSOURCE_LSE: frequency = LSE_VALUE; break; + case RCC_LPUART1_CLKSOURCE_16M: default: - frequency = HSE_VALUE / 2; + { + /* When 16M clock is selected, its source depends on HSE selection: + * - Direct HSE: HSE / 3 + * - RC64MPLL path: HSE / 4 + */ + if (LL_RCC_DIRECT_HSE_IsEnabled() != 0U) + { + /* Direct HSE clock source selected */ + frequency = HSE_VALUE / 3U; + } + else + { + /* RC64MPLL clock source selected */ + frequency = HSE_VALUE / 4U; + } break; + } } break; #endif /* RCC_CFGR_LPUCLKSEL */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_smartcard.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_smartcard.c index 4ba6363d21..9f5343d85e 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_smartcard.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_smartcard.c @@ -2388,14 +2388,6 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard ((uint32_t)hsmartcard->Init.WordLength)); MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); - /*-------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = hsmartcard->Init.StopBits; - /* Synchronous mode is activated by default */ - tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; - tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit; - tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable; - MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); - /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure * - one-bit sampling method versus three samples' majority rule @@ -2417,6 +2409,14 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos)); MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg); + /*-------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = hsmartcard->Init.StopBits; + /* Synchronous mode is activated by default */ + tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; + tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit; + tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable; + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); + /*-------------------------- USART RTOR Configuration ----------------------*/ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos); if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE) diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_spi.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_spi.c index b9794a53f4..20110527ab 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_spi.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_spi.c @@ -44,7 +44,8 @@ (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream/Channel (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. @@ -190,7 +191,8 @@ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). @note - (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and + HAL_SPI_TransmitReceive_DMA() (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() @@ -813,12 +815,12 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @brief Transmit an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent - * @param Timeout Timeout duration + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; uint16_t initial_TxXferCount; @@ -846,7 +848,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -885,7 +887,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -895,7 +897,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -919,13 +921,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr ++; hspi->TxXferCount--; } @@ -938,13 +940,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -999,10 +1001,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint * @brief Receive an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be received - * @param Timeout Timeout duration + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received + * @param Timeout Timeout duration in ms * @retval HAL status + * @note In master mode, if the direction is set to SPI_DIRECTION_2LINES + * the receive buffer is written to data register (DR) to generate + * clock pulses and receive data */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { @@ -1018,6 +1023,11 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 return HAL_BUSY; } + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1028,11 +1038,6 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ __HAL_LOCK(hspi); @@ -1241,14 +1246,14 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 * @brief Transmit and Receive an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received - * @param Timeout Timeout duration + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received + * @param Timeout Timeout duration in ms * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; @@ -1283,7 +1288,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD #endif /* USE_SPI_CRC */ if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { return HAL_BUSY; } @@ -1307,7 +1313,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferCount = Size; hspi->RxXferSize = Size; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferCount = Size; hspi->TxXferSize = Size; @@ -1347,7 +1353,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -1370,7 +1376,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ @@ -1414,13 +1420,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -1445,13 +1451,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -1590,11 +1596,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD * @brief Transmit an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { /* Check Direction parameter */ @@ -1617,7 +1623,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1672,8 +1678,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u * @brief Receive an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) @@ -1684,6 +1690,11 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui return HAL_BUSY; } + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1692,11 +1703,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui } - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ __HAL_LOCK(hspi); @@ -1775,12 +1781,13 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; @@ -1793,7 +1800,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { return HAL_BUSY; } @@ -1814,7 +1822,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -1882,11 +1890,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p * @brief Transmit an amount of data in non-blocking mode with DMA. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { /* Check tx dma handle */ @@ -1911,7 +1919,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -2002,9 +2010,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer + * @param pData pointer to data buffer (u8 or u16 data elements) * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size amount of data to be sent + * @param Size amount of data elements (u8 or u16) to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) @@ -2017,6 +2025,11 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u return HAL_BUSY; } + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -2028,11 +2041,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); } - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ __HAL_LOCK(hspi); @@ -2141,13 +2149,13 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size amount of data to be sent + * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { uint32_t tmp_mode; @@ -2165,7 +2173,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { return HAL_BUSY; } @@ -2186,7 +2195,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -2412,7 +2421,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2445,7 +2455,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2700,9 +2711,11 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode = HAL_OK; /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback(): when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback() */ /* Abort the SPI DMA tx Stream/Channel */ @@ -2992,7 +3005,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI state */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) { /* Return SPI handle state */ return hspi->State; @@ -3004,7 +3017,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI error code in bitmap format */ -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) { /* Return SPI ErrorCode */ return hspi->ErrorCode; @@ -3031,7 +3044,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; /* Init tickstart for timeout management*/ @@ -3088,7 +3101,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3205,7 +3218,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3243,7 +3256,8 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) } else { - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, + tickstart) != HAL_OK) { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); @@ -3305,7 +3319,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Tx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3323,7 +3337,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Rx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3341,7 +3355,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user TxRx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3359,7 +3373,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); @@ -3382,7 +3396,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) */ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->RxXferCount = 0U; hspi->TxXferCount = 0U; @@ -3404,7 +3418,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->hdmatx->XferAbortCallback = NULL; @@ -3420,7 +3434,8 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3470,7 +3485,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); @@ -3487,7 +3502,8 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3623,14 +3639,14 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /* Transmit data in packing Bit mode */ if (hspi->TxXferCount >= 2U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } /* Transmit data in 8 Bit mode */ else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -3724,7 +3740,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3877,7 +3893,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -3903,7 +3919,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3982,7 +3998,10 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, { tmp_timeout = 0U; } - count--; + else + { + count--; + } } } @@ -4005,7 +4024,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; - __IO uint8_t *ptmpreg8; + __IO const uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; /* Adjust Timeout value in case of end of transfer */ @@ -4064,7 +4083,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, { tmp_timeout = 0U; } - count--; + else + { + count--; + } } } @@ -4360,7 +4382,8 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4403,7 +4426,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4432,7 +4456,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_timebase_tim_template.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_timebase_tim_template.c index a2a8e3df3b..08eb62cf13 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_timebase_tim_template.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_timebase_tim_template.c @@ -55,6 +55,9 @@ extern TIM_HandleTypeDef TimHandle; TIM_HandleTypeDef TimHandle; /* Private function prototypes -----------------------------------------------*/ void TIM1_IRQHandler(void); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) +void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Private functions ---------------------------------------------------------*/ /** @@ -143,7 +146,11 @@ void HAL_ResumeTick(void) * @param htim : TIM handle * @retval None */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) +void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +#else void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { HAL_IncTick(); } diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_uart.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_uart.c index 60a762fa94..083dc4b25f 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_uart.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_uart.c @@ -644,8 +644,6 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; - __HAL_UART_DISABLE(huart); - huart->Instance->CR1 = 0x0U; huart->Instance->CR2 = 0x0U; huart->Instance->CR3 = 0x0U; @@ -3684,6 +3682,8 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { + huart->TxXferCount = 0U; + /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -3734,6 +3734,8 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { + huart->RxXferCount = 0U; + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -3760,6 +3762,8 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + huart->RxXferCount = 0; + /* Check current nb of data still to be received on DMA side. DMA Normal mode, remaining nb of data will be 0 DMA Circular mode, remaining nb of data is reset to RxXferSize */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_gpio.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_gpio.c index 2ab0d9b026..31d5fad001 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_gpio.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_gpio.c @@ -52,7 +52,7 @@ /** @addtogroup GPIO_LL_Private_Macros * @{ */ -#define IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) +#define IS_LL_GPIO_PIN(__VALUE__) (((0x00U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) #define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ @@ -153,12 +153,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru pinpos = 0; /* Configure the port pins */ - while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u) + while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00U) { /* Get current io position */ - currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos); + currentpin = (GPIO_InitStruct->Pin) & (0x00000001UL << pinpos); - if (currentpin != 0x00u) + if (currentpin != 0x00U) { if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) { diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_spi.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_spi.c index 5c25954c93..0aa16df8b5 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_spi.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_spi.c @@ -130,7 +130,7 @@ * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx) { ErrorStatus status = ERROR; @@ -167,8 +167,9 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /** * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in SPI configuration registers can only be written when the + * SPI is disabled (SPI_CR1_SPE bit = 0), SPI peripheral should be in disabled state prior + * calling this function. Otherwise, ERROR result will be returned. * @param SPIx SPI Instance * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure * @retval An ErrorStatus enumeration value. (Return always SUCCESS) @@ -238,10 +239,8 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) status = SUCCESS; } -#if defined (SPI_I2S_SUPPORT) /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); -#endif /* SPI_I2S_SUPPORT */ return status; } @@ -278,7 +277,6 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) * @} */ -#if defined(SPI_I2S_SUPPORT) /** @addtogroup I2S_LL * @{ */ @@ -355,7 +353,7 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx) { return LL_SPI_DeInit(SPIx); } @@ -542,7 +540,6 @@ void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_ /** * @} */ -#endif /* SPI_I2S_SUPPORT */ #endif /* defined (SPI1) || defined (SPI3) */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_utils.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_utils.c index c0a7af3844..440eb296c7 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_utils.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_utils.c @@ -21,11 +21,6 @@ #include "stm32wl3x_ll_rcc.h" #include "stm32wl3x_ll_system.h" #include "stm32wl3x_ll_pwr.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /** @addtogroup STM32WL3x_LL_Driver * @{ diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 873df05750..376a7251af 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -23,7 +23,7 @@ * STM32WB0: 1.5.0 * STM32WBA: 1.10.0 * STM32WL: 1.4.0 - * STM32WL3: 1.3.1 + * STM32WL3: 1.5.0 Release notes of each STM32YYxx HAL Drivers available here: From bfe639c6b5ef9c7a19b9e71a7f65a7ea31ce934f Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Jul 2026 14:41:14 +0200 Subject: [PATCH 3/7] system(wl3): update STM32WL3x CMSIS Drivers to v1.5.0 Included in STM32CubeWL3 FW v1.5.0 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32WL3x/Include/stm32wl3rx.h | 61 ++++-- .../Device/ST/STM32WL3x/Include/stm32wl3x.h | 6 +- .../Device/ST/STM32WL3x/Include/stm32wl3xx.h | 61 ++++-- .../CMSIS/Device/ST/STM32WL3x/LICENSE.md | 2 +- .../CMSIS/Device/ST/STM32WL3x/README.md | 2 +- .../Device/ST/STM32WL3x/Release_Notes.html | 105 +++++++--- .../Device/ST/STM32WL3x/Release_Notes.md | 184 ++++++++++++++++++ .../Templates/gcc/linker/STM32WL33x8_flash.ld | 18 -- .../Templates/gcc/linker/STM32WL33xB_flash.ld | 18 -- .../Templates/gcc/linker/STM32WL33xC_flash.ld | 18 -- .../Templates/gcc/linker/STM32WL3Rx8_flash.ld | 18 -- .../Templates/gcc/linker/STM32WL3RxB_flash.ld | 18 -- .../Templates/gcc/linker/stm32wl30x8_flash.ld | 173 ++++++++++++++++ .../Templates/gcc/linker/stm32wl30xB_flash.ld | 173 ++++++++++++++++ .../Templates/gcc/linker/stm32wl31x8_flash.ld | 173 ++++++++++++++++ .../Templates/gcc/linker/stm32wl31xB_flash.ld | 173 ++++++++++++++++ .../Templates/gcc/linker/stm32wl3rxx_flash.ld | 18 -- .../Templates/gcc/linker/stm32wl3xx_flash.ld | 18 -- .../Source/Templates/gcc/startup_stm32wl3xx.s | 2 - .../Source/Templates/system_stm32wl3x.c | 11 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 21 files changed, 1049 insertions(+), 205 deletions(-) create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WL3x/Release_Notes.md create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl30x8_flash.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl30xB_flash.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl31x8_flash.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl31xB_flash.ld diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3rx.h b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3rx.h index b40527bbc5..6ba8690530 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3rx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3rx.h @@ -398,7 +398,7 @@ typedef struct{ /*!< PWR Structure */ __IO uint32_t RESERVED2[10]; __IO uint32_t DBGR; /*!< (@ 0x00000084) DBGR register */ __IO uint32_t EXTSRR; /*!< (@ 0x00000088) EXTSRR register */ - __IO uint32_t RESERVED3; + __IO uint32_t DBGSMPS; /*!< (@ 0x0000008C) DBGSMPS register */ __IO uint32_t TRIMR; /*!< (@ 0x00000090) TRIMR register */ __IO uint32_t ENGTRIM; /*!< (@ 0x00000094) ENGTRIM register */ __IO uint32_t RESERVED4[2]; @@ -702,7 +702,7 @@ typedef struct{ /*!< MR_SUBG_RADIO Structure */ __IO uint32_t IQC_CTRL1; /*!< (@ 0x00000044) IQC_CTRL1 register */ __IO uint32_t IQC_CTRL2; /*!< (@ 0x00000048) IQC_CTRL2 register */ __IO uint32_t IQC_CTRL3; /*!< (@ 0x0000004C) IQC_CTRL3 register */ - __IO uint32_t RESERVED; + __IO uint32_t AGC_ANA_ENG; /*!< (@ 0x00000050) AGC_ANA_ENG register */ __IO uint32_t AGC0_CTRL; /*!< (@ 0x00000054) AGC0_CTRL register */ __IO uint32_t AGC1_CTRL; /*!< (@ 0x00000058) AGC1_CTRL register */ __IO uint32_t AGC2_CTRL; /*!< (@ 0x0000005C) AGC2_CTRL register */ @@ -906,9 +906,9 @@ typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure */ /*!< Peripheral memory map */ #define APB0PERIPH_BASE PERIPH_BASE -#define APB1PERIPH_BASE (PERIPH_BASE + 0x01000000LU) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x08000000LU) -#define APB2PERIPH_BASE (PERIPH_BASE + 0x09000000LU) +#define APB1PERIPH_BASE (PERIPH_BASE + 0x01000000UL) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x08000000UL) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x09000000UL) /*!< APB0 peripherals */ @@ -7516,6 +7516,19 @@ typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure */ #define PWR_EXTSRR_DEEPSTOPF_Msk (0x200UL) /*!< PWR EXTSRR: DEEPSTOPF (Bitfield-Mask: 0x01) */ #define PWR_EXTSRR_DEEPSTOPF PWR_EXTSRR_DEEPSTOPF_Msk +/* ===================================================== DBGSMPS =====================================================*/ +#define PWR_DBGSMPS_BOF_CUR_SEL_Pos (14UL) /*! - + @@ -34,7 +34,7 @@

        Release Notes for

        STM32WL3xx CMSIS

        -

        Copyright © 2024-2025 STMicroelectronics
        +

        Copyright © 2024-2026 STMicroelectronics

        @@ -53,20 +53,26 @@

        Purpose

        • Templates/system_stm32wl3x.c contains the initialization code referred as SystemInit.
          • -
        • Startup files are provided as example for EWARM©.
          • -
        • Linker files are provided as example for EWARM©.
          • +
        • Startup files are provided as example for EWARM©, MDK-ARM© and +STM32CubeIDE.
          • +
        • Linker files are provided as example for EWARM©, MDK-ARM© and +STM32CubeIDE.

    Update history

    - - + +

    Main Changes

      -
    • Added missing I2S support on WL3Rx devices (stm32wl3rx.h)
      • +
    • ENGTRIM2 register removed.
      • +
    • DBGSMPS register exposed.
      • +
    • System initialization template file updated, adding a macro to skip +CPU context restore.
      • +
    • Added linker file templates for WL30xx and WL31xx devices.

    Known Limitations

      @@ -84,11 +90,62 @@

      Supported Devices and boards

    + + +
    +

    Main Changes

    +
      +
    • AGC_ANA_ENG register exposed.
      • +
    • typo fixed on a register bit macro (“nAND” replaced by “NAND”)
      • +
    +

    Known Limitations

    +
      +
    • None
      • +
    +

    Development Toolchains +and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1
      • +
    +

    Supported Devices and +boards

    +
      +
    • STM32WL3xx devices
      • +
    +
    +
    +
    + + +
    +

    Main Changes

    +
      +
    • Added missing I2S support on WL3Rx devices (stm32wl3rx.h)
      • +
    +

    Known Limitations

    +
      +
    • None
      • +
    +

    Development Toolchains +and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1
      • +
    +

    Supported Devices and +boards

    +
      +
    • STM32WL3xx devices
      • +
    +
    +
    +
    -

    Main Changes

    +

    Main Changes

    • Added support to STM32WL3Rx product line.
    • [LCSC] LCSC_VER register removed from the accessible register list, @@ -98,16 +155,16 @@

      Main Changes

    • [MRSUBG] RSSI_FLT bit #3 renamed to FREEZE_SYNC_ON_SYNC_OOK_PEAK_DECAY
    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Development Toolchains +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1
    -

    Supported Devices and +

    Supported Devices and boards

    • STM32WL3xx devices
      • @@ -119,7 +176,7 @@

      Supported Devices and
      -

      Main Changes

      +

      Main Changes

      • Documentation based on jQuery 1.7.1 removed
      @@ -129,17 +186,17 @@

      Contents

    • Renamed some interrupt to improve clarity and consistency
    • Added FQCY_BAND_ID bits definition for RF_INFO_OUT register

    -

    Known Limitations

    +

    Known Limitations

    • CMSIS devices files are delivered “as is” and have not been fully validated
    -

    Development Toolchains +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1
    -

    Supported Devices and +

    Supported Devices and boards

    • STM32WL3xx devices
      • @@ -151,7 +208,7 @@

      Supported Devices and
      -

      Main Changes

      +

      Main Changes

      Release

      • Release of CMSIS for STM32WL3xx devices
        • @@ -160,17 +217,17 @@

        Contents

        • CMSIS devices files for STM32WL3xx
        -

        Known Limitations

        +

        Known Limitations

        • CMSIS devices files are delivered “as is” and have not been fully validated
        -

        Development Toolchains +

        Development Toolchains and Compilers

        • IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1
        -

        Supported Devices and +

        Supported Devices and boards

        • STM32WL3xx devices
          • @@ -182,7 +239,7 @@

          Supported Devices and
          -

          Main Changes

          +

          Main Changes

          First Release

          • First Official Release of CMSIS for STM32WL33x devices
            • @@ -191,17 +248,17 @@

            Contents

            • CMSIS devices files for STM32WL33x
            -

            Known Limitations

            +

            Known Limitations

            • CMSIS devices files are delivered “as is” and have not been fully validated
            -

            Development Toolchains +

            Development Toolchains and Compilers

            • IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1
            -

            Supported Devices and +

            Supported Devices and boards

            • STM32WL33x devices
              • diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Release_Notes.md b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Release_Notes.md new file mode 100644 index 0000000000..2d5811994a --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Release_Notes.md @@ -0,0 +1,184 @@ + + +# Release Notes for +# STM32WL3xx CMSIS +Copyright © 2024-2026 STMicroelectronics\ + +[![ST logo](_htmresc/st_logo_2020.png)](https://www.st.com) + +# Purpose + +This driver provides the CMSIS device for the STM32WL3xx products. This covers + +- STM32WL33x devices +- STM32WL3Rx devices + +This driver is composed of the description of the registers under "Include" directory. + +Various template files are provided to easily build an application. They can be adapted to fit applications requirements. + +- Templates/system_stm32wl3x.c contains the initialization code referred as SystemInit. +- Startup files are provided as example for EWARM©, MDK-ARM© and STM32CubeIDE. +- Linker files are provided as example for EWARM©, MDK-ARM© and STM32CubeIDE. + + +# Update history + + +
              + +## Main Changes +- ENGTRIM2 register removed. +- DBGSMPS register exposed. +- System initialization template file updated, adding a macro to skip CPU context restore. +- Added linker file templates for WL30xx and WL31xx devices. + +## Known Limitations +- None + +## Development Toolchains and Compilers +- IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1 + +## Supported Devices and boards +- STM32WL3xx devices +
              + + +
              + +## Main Changes +- AGC_ANA_ENG register exposed. +- typo fixed on a register bit macro ("nAND" replaced by "NAND") + +## Known Limitations +- None + +## Development Toolchains and Compilers +- IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1 + +## Supported Devices and boards +- STM32WL3xx devices +
              + + +
              + +## Main Changes +- Added missing I2S support on WL3Rx devices (stm32wl3rx.h) + +## Known Limitations +- None + +## Development Toolchains and Compilers +- IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1 + +## Supported Devices and boards +- STM32WL3xx devices + +
              + + +
              + +## Main Changes +- Added support to STM32WL3Rx product line. +- [LCSC] LCSC_VER register removed from the accessible register list, as it is Non-User. +- [LCSC] Fixed a typo on an LCSC register name (COMP_CTN -> COMP_CNT) +- [MRSUBG] RSSI_FLT bit #3 renamed to FREEZE_SYNC_ON_SYNC_OOK_PEAK_DECAY + +## Known Limitations +- None + +## Development Toolchains and Compilers +- IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1 + +## Supported Devices and boards +- STM32WL3xx devices + +
              + + +
              + +## Main Changes +- Documentation based on jQuery 1.7.1 removed + +## Contents + +- Add PULSETRIM bits definition in CMSIS header files +- Renamed some interrupt to improve clarity and consistency +- Added FQCY_BAND_ID bits definition for RF_INFO_OUT register + +## Known Limitations + +- CMSIS devices files are delivered "as is" and have not been fully validated + +## Development Toolchains and Compilers + +- IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1 + +## Supported Devices and boards + +- STM32WL3xx devices + +
              + + +
              + +## Main Changes + +### Release + +- Release of CMSIS for STM32WL3xx devices + +## Contents + +- CMSIS devices files for STM32WL3xx + +## Known Limitations + +- CMSIS devices files are delivered "as is" and have not been fully validated + +## Development Toolchains and Compilers + +- IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1 + +## Supported Devices and boards + +- STM32WL3xx devices + +
              + + +
              + +## Main Changes + +### First Release + +- First Official Release of CMSIS for STM32WL33x devices + +## Contents + +- CMSIS devices files for STM32WL33x + +## Known Limitations + +- CMSIS devices files are delivered "as is" and have not been fully validated + +## Development Toolchains and Compilers + +- IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1 + +## Supported Devices and boards + +- STM32WL33x devices + +
              + + +For complete documentation on STM32 Microcontrollers , visit: http://www.st.com/stm32 + +*This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.* +Info \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33x8_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33x8_flash.ld index a7f206c3a2..a30cc9c415 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33x8_flash.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33x8_flash.ld @@ -27,10 +27,6 @@ STM32WL3x memory map | | | FLASH (64K) | +-----------------------+ 0x10040000 -| | -+-----------------------| 0x100017FF -| ROM (6K) | -+-----------------------+ 0x10000000 */ @@ -42,10 +38,6 @@ _MEMORY_FLASH_BEGIN_ = 0x10040000; _MEMORY_FLASH_SIZE_ = 0x10000; /* 64KB */ _MEMORY_FLASH_END_ = 0x1004FFFF; -_MEMORY_ROM_BEGIN_ = 0x10000000; -_MEMORY_ROM_SIZE_ = 0x01800; /* 6KB */ -_MEMORY_ROM_END_ = 0x100017FF; - MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); @@ -66,7 +58,6 @@ MEMORY REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE - REGION_ROM (rx) : ORIGIN = _MEMORY_ROM_BEGIN_, LENGTH = _MEMORY_ROM_SIZE_ } /* Define output sections */ @@ -170,15 +161,6 @@ SECTIONS _estack = .; /* define a global symbol at stack end */ . = ALIGN(4); } > REGION_RAM - - - .rom_info (NOLOAD) : - { - . = ALIGN(4); - KEEP(*(.rom_info)) - . = ALIGN(4); - } >REGION_ROM - /* Remove information from the standard libraries */ /DISCARD/ : { diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33xB_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33xB_flash.ld index 6f376ad4fb..131cf768ef 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33xB_flash.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33xB_flash.ld @@ -27,10 +27,6 @@ STM32WL3x memory map | | | FLASH (128K) | +-----------------------+ 0x10040000 -| | -+-----------------------| 0x100017FF -| ROM (6K) | -+-----------------------+ 0x10000000 */ @@ -42,10 +38,6 @@ _MEMORY_FLASH_BEGIN_ = 0x10040000; _MEMORY_FLASH_SIZE_ = 0x20000; /* 128KB */ _MEMORY_FLASH_END_ = 0x1005FFFF; -_MEMORY_ROM_BEGIN_ = 0x10000000; -_MEMORY_ROM_SIZE_ = 0x01800; /* 6KB */ -_MEMORY_ROM_END_ = 0x100017FF; - MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); @@ -66,7 +58,6 @@ MEMORY REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE - REGION_ROM (rx) : ORIGIN = _MEMORY_ROM_BEGIN_, LENGTH = _MEMORY_ROM_SIZE_ } /* Define output sections */ @@ -170,15 +161,6 @@ SECTIONS _estack = .; /* define a global symbol at stack end */ . = ALIGN(4); } > REGION_RAM - - - .rom_info (NOLOAD) : - { - . = ALIGN(4); - KEEP(*(.rom_info)) - . = ALIGN(4); - } >REGION_ROM - /* Remove information from the standard libraries */ /DISCARD/ : { diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33xC_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33xC_flash.ld index e10273958b..c62b6d76d0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33xC_flash.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33xC_flash.ld @@ -27,10 +27,6 @@ STM32WL3x memory map | | | FLASH (256K) | +-----------------------+ 0x10040000 -| | -+-----------------------| 0x100017FF -| ROM (6K) | -+-----------------------+ 0x10000000 */ @@ -42,10 +38,6 @@ _MEMORY_FLASH_BEGIN_ = 0x10040000; _MEMORY_FLASH_SIZE_ = 0x40000; /* 256KB */ _MEMORY_FLASH_END_ = 0x1007FFFF; -_MEMORY_ROM_BEGIN_ = 0x10000000; -_MEMORY_ROM_SIZE_ = 0x01800; /* 6KB */ -_MEMORY_ROM_END_ = 0x100017FF; - MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); @@ -66,7 +58,6 @@ MEMORY REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE - REGION_ROM (rx) : ORIGIN = _MEMORY_ROM_BEGIN_, LENGTH = _MEMORY_ROM_SIZE_ } /* Define output sections */ @@ -170,15 +161,6 @@ SECTIONS _estack = .; /* define a global symbol at stack end */ . = ALIGN(4); } > REGION_RAM - - - .rom_info (NOLOAD) : - { - . = ALIGN(4); - KEEP(*(.rom_info)) - . = ALIGN(4); - } >REGION_ROM - /* Remove information from the standard libraries */ /DISCARD/ : { diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL3Rx8_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL3Rx8_flash.ld index cfa191b9dd..b894d83310 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL3Rx8_flash.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL3Rx8_flash.ld @@ -27,10 +27,6 @@ STM32WL3x memory map | | | FLASH (64K) | +-----------------------+ 0x10040000 -| | -+-----------------------| 0x100017FF -| ROM (6K) | -+-----------------------+ 0x10000000 */ @@ -42,10 +38,6 @@ _MEMORY_FLASH_BEGIN_ = 0x10040000; _MEMORY_FLASH_SIZE_ = 0x10000; /* 64KB */ _MEMORY_FLASH_END_ = 0x1004FFFF; -_MEMORY_ROM_BEGIN_ = 0x10000000; -_MEMORY_ROM_SIZE_ = 0x01800; /* 6KB */ -_MEMORY_ROM_END_ = 0x100017FF; - MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); @@ -66,7 +58,6 @@ MEMORY REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE - REGION_ROM (rx) : ORIGIN = _MEMORY_ROM_BEGIN_, LENGTH = _MEMORY_ROM_SIZE_ } /* Define output sections */ @@ -170,15 +161,6 @@ SECTIONS _estack = .; /* define a global symbol at stack end */ . = ALIGN(4); } > REGION_RAM - - - .rom_info (NOLOAD) : - { - . = ALIGN(4); - KEEP(*(.rom_info)) - . = ALIGN(4); - } >REGION_ROM - /* Remove information from the standard libraries */ /DISCARD/ : { diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL3RxB_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL3RxB_flash.ld index 98834d5850..c99d06b671 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL3RxB_flash.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL3RxB_flash.ld @@ -27,10 +27,6 @@ STM32WL3x memory map | | | FLASH (128K) | +-----------------------+ 0x10040000 -| | -+-----------------------| 0x100017FF -| ROM (6K) | -+-----------------------+ 0x10000000 */ @@ -42,10 +38,6 @@ _MEMORY_FLASH_BEGIN_ = 0x10040000; _MEMORY_FLASH_SIZE_ = 0x20000; /* 128KB */ _MEMORY_FLASH_END_ = 0x1005FFFF; -_MEMORY_ROM_BEGIN_ = 0x10000000; -_MEMORY_ROM_SIZE_ = 0x01800; /* 6KB */ -_MEMORY_ROM_END_ = 0x100017FF; - MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); @@ -66,7 +58,6 @@ MEMORY REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE - REGION_ROM (rx) : ORIGIN = _MEMORY_ROM_BEGIN_, LENGTH = _MEMORY_ROM_SIZE_ } /* Define output sections */ @@ -170,15 +161,6 @@ SECTIONS _estack = .; /* define a global symbol at stack end */ . = ALIGN(4); } > REGION_RAM - - - .rom_info (NOLOAD) : - { - . = ALIGN(4); - KEEP(*(.rom_info)) - . = ALIGN(4); - } >REGION_ROM - /* Remove information from the standard libraries */ /DISCARD/ : { diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl30x8_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl30x8_flash.ld new file mode 100644 index 0000000000..b894d83310 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl30x8_flash.ld @@ -0,0 +1,173 @@ +/******************************************************************************* +* STM32WL3x generic linker file for GCC +* Main linker variables to control it are: +* +* MEMORY_FLASH_APP_SIZE: define the size of the application in case not all the flash is needed. +* Default value is: 64KB +* +* MEMORY_FLASH_APP_OFFSET: define the offset of the application. +* Default value is: 0 offset +* +* MEMORY_RAM_APP_OFFSET: define the offset in RAM from which variables can be +* allocated. +* +*******************************************************************************/ + +/******************************************************************************* +* Memory Definitions +*******************************************************************************/ +/* +STM32WL3x memory map ++-----------------------+ 0x20001FFF +| RAM (8K) | ++-----------------------+ 0x20000000 +| | +| | ++-----------------------+ 0x1004FFFF +| | +| FLASH (64K) | ++-----------------------+ 0x10040000 +*/ + + +_MEMORY_RAM_BEGIN_ = 0x20000000; +_MEMORY_RAM_SIZE_ = 0x2000; /* 8KB */ +_MEMORY_RAM_END_ = 0x20001FFF; + +_MEMORY_FLASH_BEGIN_ = 0x10040000; +_MEMORY_FLASH_SIZE_ = 0x10000; /* 64KB */ +_MEMORY_FLASH_END_ = 0x1004FFFF; + + +MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; +MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); +RESET_MANAGER_SIZE = DEFINED(RESET_MANAGER_SIZE) ? (RESET_MANAGER_SIZE) : (0x800) ; + + +/* Entry Point */ +ENTRY(Reset_Handler) + + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x000; /* required amount of heap */ +_Min_Stack_Size = 0xC00; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ + REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET + REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE +} + +/* Define output sections */ +SECTIONS +{ + + /* The startup code goes first into FLASH */ + .intvec (ORIGIN(REGION_FLASH)) : + { + . = ALIGN(4); + + KEEP(*(.intvec)) /* Startup code */ + + . = ALIGN(4); + } >REGION_FLASH + + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + + KEEP(*(.cmd_call_table)) + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(i.*) /* i.* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.constdata) + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + + . = ALIGN(4); + _etext = .; + } >REGION_FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* RAM preamble, uninitialized */ + .ram_preamble 0x20000004 (NOLOAD) : + { + KEEP(*(.ram_vr)) + } >REGION_RAM AT> REGION_FLASH + + /* RAM preamble, unininitialized */ + .ram_preamble_2 0x20000034 (NOLOAD) : + { + KEEP(*(.crash_info_ram_vr)) + } >REGION_RAM + /* Uninitialized data section */ + + .bss DEFINED(MEMORY_RAM_APP_OFFSET) ? (ORIGIN(REGION_RAM) + MEMORY_RAM_APP_OFFSET) : . : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start */ + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + } >REGION_RAM + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >REGION_RAM AT> REGION_FLASH + + /* Data section that will not be initialized to any value. */ + .noinit (NOLOAD): + { + . = ALIGN(4); + *(.noinit) + . = ALIGN(4); + } >REGION_RAM + + .heap (NOLOAD): + { + . = ALIGN(4); + _sheap = .; + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = ALIGN(4); + _eheap = .; + } >REGION_RAM + + /* This is to emulate place at end of IAR linker */ + CSTACK (ORIGIN(REGION_RAM) + LENGTH(REGION_RAM) - _Min_Stack_Size) (NOLOAD) : + { + . = ALIGN(4); + . = . + _Min_Stack_Size; + . = ALIGN(4); + _estack = .; /* define a global symbol at stack end */ + . = ALIGN(4); + } > REGION_RAM + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl30xB_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl30xB_flash.ld new file mode 100644 index 0000000000..c99d06b671 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl30xB_flash.ld @@ -0,0 +1,173 @@ +/******************************************************************************* +* STM32WL3x generic linker file for GCC +* Main linker variables to control it are: +* +* MEMORY_FLASH_APP_SIZE: define the size of the application in case not all the flash is needed. +* Default value is: 128KB +* +* MEMORY_FLASH_APP_OFFSET: define the offset of the application. +* Default value is: 0 offset +* +* MEMORY_RAM_APP_OFFSET: define the offset in RAM from which variables can be +* allocated. +* +*******************************************************************************/ + +/******************************************************************************* +* Memory Definitions +*******************************************************************************/ +/* +STM32WL3x memory map ++-----------------------+ 0x20003FFF +| RAM (16K) | ++-----------------------+ 0x20000000 +| | +| | ++-----------------------+ 0x1005FFFF +| | +| FLASH (128K) | ++-----------------------+ 0x10040000 +*/ + + +_MEMORY_RAM_BEGIN_ = 0x20000000; +_MEMORY_RAM_SIZE_ = 0x4000; /* 16KB */ +_MEMORY_RAM_END_ = 0x20003FFF; + +_MEMORY_FLASH_BEGIN_ = 0x10040000; +_MEMORY_FLASH_SIZE_ = 0x20000; /* 128KB */ +_MEMORY_FLASH_END_ = 0x1005FFFF; + + +MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; +MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); +RESET_MANAGER_SIZE = DEFINED(RESET_MANAGER_SIZE) ? (RESET_MANAGER_SIZE) : (0x800) ; + + +/* Entry Point */ +ENTRY(Reset_Handler) + + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x000; /* required amount of heap */ +_Min_Stack_Size = 0xC00; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ + REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET + REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE +} + +/* Define output sections */ +SECTIONS +{ + + /* The startup code goes first into FLASH */ + .intvec (ORIGIN(REGION_FLASH)) : + { + . = ALIGN(4); + + KEEP(*(.intvec)) /* Startup code */ + + . = ALIGN(4); + } >REGION_FLASH + + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + + KEEP(*(.cmd_call_table)) + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(i.*) /* i.* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.constdata) + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + + . = ALIGN(4); + _etext = .; + } >REGION_FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* RAM preamble, uninitialized */ + .ram_preamble 0x20000004 (NOLOAD) : + { + KEEP(*(.ram_vr)) + } >REGION_RAM AT> REGION_FLASH + + /* RAM preamble, unininitialized */ + .ram_preamble_2 0x20000034 (NOLOAD) : + { + KEEP(*(.crash_info_ram_vr)) + } >REGION_RAM + /* Uninitialized data section */ + + .bss DEFINED(MEMORY_RAM_APP_OFFSET) ? (ORIGIN(REGION_RAM) + MEMORY_RAM_APP_OFFSET) : . : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start */ + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + } >REGION_RAM + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >REGION_RAM AT> REGION_FLASH + + /* Data section that will not be initialized to any value. */ + .noinit (NOLOAD): + { + . = ALIGN(4); + *(.noinit) + . = ALIGN(4); + } >REGION_RAM + + .heap (NOLOAD): + { + . = ALIGN(4); + _sheap = .; + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = ALIGN(4); + _eheap = .; + } >REGION_RAM + + /* This is to emulate place at end of IAR linker */ + CSTACK (ORIGIN(REGION_RAM) + LENGTH(REGION_RAM) - _Min_Stack_Size) (NOLOAD) : + { + . = ALIGN(4); + . = . + _Min_Stack_Size; + . = ALIGN(4); + _estack = .; /* define a global symbol at stack end */ + . = ALIGN(4); + } > REGION_RAM + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl31x8_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl31x8_flash.ld new file mode 100644 index 0000000000..b894d83310 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl31x8_flash.ld @@ -0,0 +1,173 @@ +/******************************************************************************* +* STM32WL3x generic linker file for GCC +* Main linker variables to control it are: +* +* MEMORY_FLASH_APP_SIZE: define the size of the application in case not all the flash is needed. +* Default value is: 64KB +* +* MEMORY_FLASH_APP_OFFSET: define the offset of the application. +* Default value is: 0 offset +* +* MEMORY_RAM_APP_OFFSET: define the offset in RAM from which variables can be +* allocated. +* +*******************************************************************************/ + +/******************************************************************************* +* Memory Definitions +*******************************************************************************/ +/* +STM32WL3x memory map ++-----------------------+ 0x20001FFF +| RAM (8K) | ++-----------------------+ 0x20000000 +| | +| | ++-----------------------+ 0x1004FFFF +| | +| FLASH (64K) | ++-----------------------+ 0x10040000 +*/ + + +_MEMORY_RAM_BEGIN_ = 0x20000000; +_MEMORY_RAM_SIZE_ = 0x2000; /* 8KB */ +_MEMORY_RAM_END_ = 0x20001FFF; + +_MEMORY_FLASH_BEGIN_ = 0x10040000; +_MEMORY_FLASH_SIZE_ = 0x10000; /* 64KB */ +_MEMORY_FLASH_END_ = 0x1004FFFF; + + +MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; +MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); +RESET_MANAGER_SIZE = DEFINED(RESET_MANAGER_SIZE) ? (RESET_MANAGER_SIZE) : (0x800) ; + + +/* Entry Point */ +ENTRY(Reset_Handler) + + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x000; /* required amount of heap */ +_Min_Stack_Size = 0xC00; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ + REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET + REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE +} + +/* Define output sections */ +SECTIONS +{ + + /* The startup code goes first into FLASH */ + .intvec (ORIGIN(REGION_FLASH)) : + { + . = ALIGN(4); + + KEEP(*(.intvec)) /* Startup code */ + + . = ALIGN(4); + } >REGION_FLASH + + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + + KEEP(*(.cmd_call_table)) + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(i.*) /* i.* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.constdata) + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + + . = ALIGN(4); + _etext = .; + } >REGION_FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* RAM preamble, uninitialized */ + .ram_preamble 0x20000004 (NOLOAD) : + { + KEEP(*(.ram_vr)) + } >REGION_RAM AT> REGION_FLASH + + /* RAM preamble, unininitialized */ + .ram_preamble_2 0x20000034 (NOLOAD) : + { + KEEP(*(.crash_info_ram_vr)) + } >REGION_RAM + /* Uninitialized data section */ + + .bss DEFINED(MEMORY_RAM_APP_OFFSET) ? (ORIGIN(REGION_RAM) + MEMORY_RAM_APP_OFFSET) : . : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start */ + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + } >REGION_RAM + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >REGION_RAM AT> REGION_FLASH + + /* Data section that will not be initialized to any value. */ + .noinit (NOLOAD): + { + . = ALIGN(4); + *(.noinit) + . = ALIGN(4); + } >REGION_RAM + + .heap (NOLOAD): + { + . = ALIGN(4); + _sheap = .; + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = ALIGN(4); + _eheap = .; + } >REGION_RAM + + /* This is to emulate place at end of IAR linker */ + CSTACK (ORIGIN(REGION_RAM) + LENGTH(REGION_RAM) - _Min_Stack_Size) (NOLOAD) : + { + . = ALIGN(4); + . = . + _Min_Stack_Size; + . = ALIGN(4); + _estack = .; /* define a global symbol at stack end */ + . = ALIGN(4); + } > REGION_RAM + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl31xB_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl31xB_flash.ld new file mode 100644 index 0000000000..c99d06b671 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl31xB_flash.ld @@ -0,0 +1,173 @@ +/******************************************************************************* +* STM32WL3x generic linker file for GCC +* Main linker variables to control it are: +* +* MEMORY_FLASH_APP_SIZE: define the size of the application in case not all the flash is needed. +* Default value is: 128KB +* +* MEMORY_FLASH_APP_OFFSET: define the offset of the application. +* Default value is: 0 offset +* +* MEMORY_RAM_APP_OFFSET: define the offset in RAM from which variables can be +* allocated. +* +*******************************************************************************/ + +/******************************************************************************* +* Memory Definitions +*******************************************************************************/ +/* +STM32WL3x memory map ++-----------------------+ 0x20003FFF +| RAM (16K) | ++-----------------------+ 0x20000000 +| | +| | ++-----------------------+ 0x1005FFFF +| | +| FLASH (128K) | ++-----------------------+ 0x10040000 +*/ + + +_MEMORY_RAM_BEGIN_ = 0x20000000; +_MEMORY_RAM_SIZE_ = 0x4000; /* 16KB */ +_MEMORY_RAM_END_ = 0x20003FFF; + +_MEMORY_FLASH_BEGIN_ = 0x10040000; +_MEMORY_FLASH_SIZE_ = 0x20000; /* 128KB */ +_MEMORY_FLASH_END_ = 0x1005FFFF; + + +MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; +MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); +RESET_MANAGER_SIZE = DEFINED(RESET_MANAGER_SIZE) ? (RESET_MANAGER_SIZE) : (0x800) ; + + +/* Entry Point */ +ENTRY(Reset_Handler) + + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x000; /* required amount of heap */ +_Min_Stack_Size = 0xC00; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ + REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET + REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE +} + +/* Define output sections */ +SECTIONS +{ + + /* The startup code goes first into FLASH */ + .intvec (ORIGIN(REGION_FLASH)) : + { + . = ALIGN(4); + + KEEP(*(.intvec)) /* Startup code */ + + . = ALIGN(4); + } >REGION_FLASH + + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + + KEEP(*(.cmd_call_table)) + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(i.*) /* i.* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.constdata) + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + + . = ALIGN(4); + _etext = .; + } >REGION_FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* RAM preamble, uninitialized */ + .ram_preamble 0x20000004 (NOLOAD) : + { + KEEP(*(.ram_vr)) + } >REGION_RAM AT> REGION_FLASH + + /* RAM preamble, unininitialized */ + .ram_preamble_2 0x20000034 (NOLOAD) : + { + KEEP(*(.crash_info_ram_vr)) + } >REGION_RAM + /* Uninitialized data section */ + + .bss DEFINED(MEMORY_RAM_APP_OFFSET) ? (ORIGIN(REGION_RAM) + MEMORY_RAM_APP_OFFSET) : . : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start */ + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + } >REGION_RAM + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >REGION_RAM AT> REGION_FLASH + + /* Data section that will not be initialized to any value. */ + .noinit (NOLOAD): + { + . = ALIGN(4); + *(.noinit) + . = ALIGN(4); + } >REGION_RAM + + .heap (NOLOAD): + { + . = ALIGN(4); + _sheap = .; + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = ALIGN(4); + _eheap = .; + } >REGION_RAM + + /* This is to emulate place at end of IAR linker */ + CSTACK (ORIGIN(REGION_RAM) + LENGTH(REGION_RAM) - _Min_Stack_Size) (NOLOAD) : + { + . = ALIGN(4); + . = . + _Min_Stack_Size; + . = ALIGN(4); + _estack = .; /* define a global symbol at stack end */ + . = ALIGN(4); + } > REGION_RAM + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl3rxx_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl3rxx_flash.ld index 98834d5850..c99d06b671 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl3rxx_flash.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl3rxx_flash.ld @@ -27,10 +27,6 @@ STM32WL3x memory map | | | FLASH (128K) | +-----------------------+ 0x10040000 -| | -+-----------------------| 0x100017FF -| ROM (6K) | -+-----------------------+ 0x10000000 */ @@ -42,10 +38,6 @@ _MEMORY_FLASH_BEGIN_ = 0x10040000; _MEMORY_FLASH_SIZE_ = 0x20000; /* 128KB */ _MEMORY_FLASH_END_ = 0x1005FFFF; -_MEMORY_ROM_BEGIN_ = 0x10000000; -_MEMORY_ROM_SIZE_ = 0x01800; /* 6KB */ -_MEMORY_ROM_END_ = 0x100017FF; - MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); @@ -66,7 +58,6 @@ MEMORY REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE - REGION_ROM (rx) : ORIGIN = _MEMORY_ROM_BEGIN_, LENGTH = _MEMORY_ROM_SIZE_ } /* Define output sections */ @@ -170,15 +161,6 @@ SECTIONS _estack = .; /* define a global symbol at stack end */ . = ALIGN(4); } > REGION_RAM - - - .rom_info (NOLOAD) : - { - . = ALIGN(4); - KEEP(*(.rom_info)) - . = ALIGN(4); - } >REGION_ROM - /* Remove information from the standard libraries */ /DISCARD/ : { diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl3xx_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl3xx_flash.ld index e10273958b..c62b6d76d0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl3xx_flash.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl3xx_flash.ld @@ -27,10 +27,6 @@ STM32WL3x memory map | | | FLASH (256K) | +-----------------------+ 0x10040000 -| | -+-----------------------| 0x100017FF -| ROM (6K) | -+-----------------------+ 0x10000000 */ @@ -42,10 +38,6 @@ _MEMORY_FLASH_BEGIN_ = 0x10040000; _MEMORY_FLASH_SIZE_ = 0x40000; /* 256KB */ _MEMORY_FLASH_END_ = 0x1007FFFF; -_MEMORY_ROM_BEGIN_ = 0x10000000; -_MEMORY_ROM_SIZE_ = 0x01800; /* 6KB */ -_MEMORY_ROM_END_ = 0x100017FF; - MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); @@ -66,7 +58,6 @@ MEMORY REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE - REGION_ROM (rx) : ORIGIN = _MEMORY_ROM_BEGIN_, LENGTH = _MEMORY_ROM_SIZE_ } /* Define output sections */ @@ -170,15 +161,6 @@ SECTIONS _estack = .; /* define a global symbol at stack end */ . = ALIGN(4); } > REGION_RAM - - - .rom_info (NOLOAD) : - { - . = ALIGN(4); - KEEP(*(.rom_info)) - . = ALIGN(4); - } >REGION_ROM - /* Remove information from the standard libraries */ /DISCARD/ : { diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s index b0ce567927..ed0d82befe 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s @@ -83,8 +83,6 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call static constructors */ - bl __libc_init_array /* Call the application's entry point.*/ bl main diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/system_stm32wl3x.c b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/system_stm32wl3x.c index 3bafa496d2..3c28f811eb 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/system_stm32wl3x.c +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/system_stm32wl3x.c @@ -96,16 +96,15 @@ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. This value must be a multiple of 0x100. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x100. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. This value must be a multiple of 0x100. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x100. */ #endif /* VECT_TAB_SRAM */ +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. + This value must be a multiple of 0x100. */ +#endif /* VECT_TAB_OFFSET */ #endif /* USER_VECT_TAB_ADDRESS */ - /******************************************************************************/ /*!< HW TRIMMING Defines */ @@ -200,12 +199,14 @@ void SystemInit(void) if ((RCC->CSR == 0) && ((PWR->IWUF != 0) || (PWR->WUFA != 0) || (PWR->WUFB != 0))) { RAM_VR.WakeupFromSleepFlag = 1; /* A wakeup from power save occurred */ +#if !defined(NO_CTX_RESTORE) CPUcontextRestore(); /* Restore the context */ /* if the context restore worked properly, we should never return here */ while(1) { NVIC_SystemReset(); } +#endif /* NO_CTX_RESTORE */ } /* Configure the Vector Table location */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 14a140c3ac..91609d0588 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -23,7 +23,7 @@ * STM32WB0: 1.4.0 * STM32WBA: 1.10.0 * STM32WL: 1.3.0 - * STM32WL3: 1.3.1 + * STM32WL3: 1.5.0 Release notes of each STM32YYxx CMSIS available here: From a1bc76f1b42c3c47f8e768c6f290f29cca352fa4 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 23 Sep 2025 14:48:50 +0200 Subject: [PATCH 4/7] fix(wl3): HAL and LL warnings Signed-off-by: Frederic Pillon --- .../Inc/stm32wl3x_ll_dma.h | 104 ++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h index b94790b322..e49d7c53f5 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h @@ -433,6 +433,7 @@ typedef struct */ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } @@ -453,6 +454,7 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } @@ -473,6 +475,7 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); } @@ -509,6 +512,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, Configuration); @@ -536,6 +540,7 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); } @@ -561,6 +566,7 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM)); } @@ -587,6 +593,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint */ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC, Mode); } @@ -610,6 +617,7 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_ */ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC)); } @@ -634,6 +642,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC, PeriphOrM2MSrcIncMode); } @@ -657,6 +666,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC)); } @@ -681,6 +691,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC, MemoryOrM2MDstIncMode); } @@ -704,6 +715,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC)); } @@ -729,6 +741,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE, PeriphOrM2MSrcDataSize); } @@ -753,6 +766,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE)); } @@ -778,6 +792,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE, MemoryOrM2MDstDataSize); } @@ -802,6 +817,7 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE)); } @@ -828,6 +844,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL, Priority); } @@ -853,6 +870,7 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL)); } @@ -877,6 +895,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint3 */ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR, DMA_CNDTR_NDT, NbData); } @@ -900,6 +919,7 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR, DMA_CNDTR_NDT)); } @@ -931,6 +951,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { + (void)DMAx; /* Direction Memory to Periph */ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) { @@ -965,6 +986,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } @@ -988,6 +1010,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) { + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress); } @@ -1009,6 +1032,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } @@ -1030,6 +1054,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } @@ -1053,6 +1078,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress); } @@ -1076,6 +1102,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } @@ -1097,6 +1124,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } @@ -1118,6 +1146,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } @@ -1140,6 +1169,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID, Request); } @@ -1161,6 +1191,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID)); } @@ -1180,6 +1211,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); } @@ -1191,6 +1223,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); } @@ -1202,6 +1235,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); } @@ -1213,6 +1247,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); } @@ -1224,6 +1259,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); } @@ -1235,6 +1271,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); } @@ -1246,6 +1283,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); } @@ -1257,6 +1295,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF8) == (DMA_ISR_GIF8)) ? 1UL : 0UL); } @@ -1268,6 +1307,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); } @@ -1279,6 +1319,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); } @@ -1290,6 +1331,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); } @@ -1301,6 +1343,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); } @@ -1312,6 +1355,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); } @@ -1323,6 +1367,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); } @@ -1334,6 +1379,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); } @@ -1345,6 +1391,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF8) == (DMA_ISR_TCIF8)) ? 1UL : 0UL); } @@ -1356,6 +1403,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); } @@ -1367,6 +1415,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); } @@ -1378,6 +1427,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); } @@ -1389,6 +1439,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); } @@ -1400,6 +1451,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); } @@ -1411,6 +1463,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); } @@ -1422,6 +1475,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); } @@ -1433,6 +1487,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF8) == (DMA_ISR_HTIF8)) ? 1UL : 0UL); } @@ -1444,6 +1499,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); } @@ -1455,6 +1511,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); } @@ -1466,6 +1523,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); } @@ -1477,6 +1535,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); } @@ -1488,6 +1547,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); } @@ -1499,6 +1559,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); } @@ -1510,6 +1571,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); } @@ -1521,6 +1583,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF8) == (DMA_ISR_TEIF8)) ? 1UL : 0UL); } @@ -1532,6 +1595,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); } @@ -1543,6 +1607,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); } @@ -1554,6 +1619,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); } @@ -1565,6 +1631,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); } @@ -1576,6 +1643,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); } @@ -1587,6 +1655,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); } @@ -1598,6 +1667,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); } @@ -1609,6 +1679,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF8); } @@ -1620,6 +1691,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); } @@ -1631,6 +1703,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); } @@ -1642,6 +1715,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); } @@ -1653,6 +1727,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); } @@ -1664,6 +1739,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); } @@ -1675,6 +1751,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); } @@ -1686,6 +1763,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); } @@ -1697,6 +1775,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF8); } @@ -1708,6 +1787,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); } @@ -1719,6 +1799,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); } @@ -1730,6 +1811,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); } @@ -1741,6 +1823,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); } @@ -1752,6 +1835,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); } @@ -1763,6 +1847,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); } @@ -1774,6 +1859,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); } @@ -1785,6 +1871,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF8); } @@ -1796,6 +1883,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); } @@ -1807,6 +1895,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); } @@ -1818,6 +1907,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); } @@ -1829,6 +1919,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); } @@ -1840,6 +1931,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); } @@ -1851,6 +1943,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); } @@ -1862,6 +1955,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); } @@ -1873,6 +1967,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF8); } @@ -1900,6 +1995,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } @@ -1920,6 +2016,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } @@ -1940,6 +2037,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } @@ -1960,6 +2058,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } @@ -1980,6 +2079,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } @@ -2000,6 +2100,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } @@ -2020,6 +2121,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); } @@ -2041,6 +2143,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); } @@ -2062,6 +2165,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); } From 922687801c043d343f75356ca8d39459766b0bb0 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 23 Sep 2025 09:50:23 +0200 Subject: [PATCH 5/7] feat(wl3): add __libc_init_array call to startup Signed-off-by: Frederic Pillon --- .../ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s | 2 ++ 1 file changed, 2 insertions(+) diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s index ed0d82befe..b0ce567927 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s @@ -83,6 +83,8 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss +/* Call static constructors */ + bl __libc_init_array /* Call the application's entry point.*/ bl main From e5d986f026695bb22744933ae3b11c94240655e1 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Jul 2026 14:44:06 +0200 Subject: [PATCH 6/7] chore(wl3): update system source Signed-off-by: Frederic Pillon --- system/STM32WL3x/system_stm32wl3x.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/system/STM32WL3x/system_stm32wl3x.c b/system/STM32WL3x/system_stm32wl3x.c index 3d000f3baa..7bb1131c8d 100644 --- a/system/STM32WL3x/system_stm32wl3x.c +++ b/system/STM32WL3x/system_stm32wl3x.c @@ -191,12 +191,14 @@ void SystemInit(void) if ((RCC->CSR == 0) && ((PWR->IWUF != 0) || (PWR->WUFA != 0) || (PWR->WUFB != 0))) { RAM_VR.WakeupFromSleepFlag = 1; /* A wakeup from power save occurred */ +#if !defined(NO_CTX_RESTORE) CPUcontextRestore(); /* Restore the context */ /* if the context restore worked properly, we should never return here */ while(1) { NVIC_SystemReset(); } +#endif /* NO_CTX_RESTORE */ } /* Configure the Vector Table location */ From 4e873ef9e00f4bfaf748c0d4f6fda3566b46dce6 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Jul 2026 14:49:18 +0200 Subject: [PATCH 7/7] chore(wl3): remove ROM info from the linker script Signed-off-by: Frederic Pillon --- variants/STM32WL3x/WL33C(8-B-C)Vx(X)/ldscript.ld | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/variants/STM32WL3x/WL33C(8-B-C)Vx(X)/ldscript.ld b/variants/STM32WL3x/WL33C(8-B-C)Vx(X)/ldscript.ld index 94ad364ef7..3a9d9d1a81 100644 --- a/variants/STM32WL3x/WL33C(8-B-C)Vx(X)/ldscript.ld +++ b/variants/STM32WL3x/WL33C(8-B-C)Vx(X)/ldscript.ld @@ -27,10 +27,6 @@ STM32WL3x memory map | | | FLASH (256K) | +-----------------------+ 0x10040000 -| | -+-----------------------| 0x100017FF -| ROM (6K) | -+-----------------------+ 0x10000000 */ @@ -42,10 +38,6 @@ _MEMORY_FLASH_BEGIN_ = 0x10040000; _MEMORY_FLASH_SIZE_ = LD_MAX_SIZE; _MEMORY_FLASH_END_ = 0x1007FFFF; -_MEMORY_ROM_BEGIN_ = 0x10000000; -_MEMORY_ROM_SIZE_ = 0x01800; -_MEMORY_ROM_END_ = 0x100017FF; - MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (LD_FLASH_OFFSET) ; MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); @@ -66,7 +58,6 @@ MEMORY RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE - REGION_ROM (rx) : ORIGIN = _MEMORY_ROM_BEGIN_, LENGTH = _MEMORY_ROM_SIZE_ } /* Define output sections */ @@ -199,13 +190,6 @@ SECTIONS . = ALIGN(4); } > RAM - .rom_info (NOLOAD) : - { - . = ALIGN(4); - KEEP(*(.rom_info)) - . = ALIGN(4); - } >REGION_ROM - /* Remove information from the standard libraries */ /DISCARD/ : {