From 1d4170ba7ae8dcf0ba69456731f2a37b958a30ac Mon Sep 17 00:00:00 2001 From: Jonathan Pallant Date: Tue, 21 Jul 2026 13:58:37 +0100 Subject: [PATCH 1/8] Bump cortex-m-rt to 0.7.6 for release --- cortex-m-rt/CHANGELOG.md | 7 +++++-- cortex-m-rt/Cargo.toml | 4 ++-- cortex-m-rt/macros/Cargo.toml | 2 +- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/cortex-m-rt/CHANGELOG.md b/cortex-m-rt/CHANGELOG.md index 0d230f65..a8ba0baa 100644 --- a/cortex-m-rt/CHANGELOG.md +++ b/cortex-m-rt/CHANGELOG.md @@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +## [v0.7.6] + - Mark `pre_init` as deprecated - Add `set_msplim` feature to conditionally set the MSPLIM register at device reset ([#580]). @@ -657,8 +659,9 @@ section size addr Initial release -[Unreleased]: https://github.com/rust-embedded/cortex-m/compare/c-m-rt-v0.7.5...HEAD -[v0.7.4]: https://github.com/rust-embedded/cortex-m/compare/c-m-rt-v0.7.4...c-m-rt-v0.7.5 +[Unreleased]: https://github.com/rust-embedded/cortex-m/compare/c-m-rt-v0.7.6...HEAD +[v0.7.6]: https://github.com/rust-embedded/cortex-m/compare/c-m-rt-v0.7.5...c-m-rt-v0.7.6 +[v0.7.5]: https://github.com/rust-embedded/cortex-m/compare/c-m-rt-v0.7.4...c-m-rt-v0.7.5 [v0.7.4]: https://github.com/rust-embedded/cortex-m/compare/c-m-rt-v0.7.3...c-m-rt-v0.7.4 [v0.7.3]: https://github.com/rust-embedded/cortex-m/compare/c-m-rt-v0.7.2...c-m-rt-v0.7.3 [v0.7.2]: https://github.com/rust-embedded/cortex-m/compare/c-m-rt-v0.7.1...c-m-rt-v0.7.2 diff --git a/cortex-m-rt/Cargo.toml b/cortex-m-rt/Cargo.toml index 99bac7ea..437d8639 100644 --- a/cortex-m-rt/Cargo.toml +++ b/cortex-m-rt/Cargo.toml @@ -7,14 +7,14 @@ license = "MIT OR Apache-2.0" name = "cortex-m-rt" readme = "README.md" repository = "https://github.com/rust-embedded/cortex-m" -version = "0.7.5" +version = "0.7.6" autoexamples = true links = "cortex-m-rt" # Prevent multiple versions of cortex-m-rt being linked edition = "2024" rust-version = "1.85" [dependencies] -cortex-m-rt-macros = { path = "macros", version = "=0.7.5" } +cortex-m-rt-macros = { path = "macros", version = "=0.7.6" } [dev-dependencies] panic-halt = "0.2.0" diff --git a/cortex-m-rt/macros/Cargo.toml b/cortex-m-rt/macros/Cargo.toml index 56c17f00..1058c5d5 100644 --- a/cortex-m-rt/macros/Cargo.toml +++ b/cortex-m-rt/macros/Cargo.toml @@ -6,7 +6,7 @@ keywords = ["arm", "cortex-m", "runtime", "startup"] license = "MIT OR Apache-2.0" name = "cortex-m-rt-macros" repository = "https://github.com/rust-embedded/cortex-m" -version = "0.7.5" +version = "0.7.6" edition = "2021" rust-version = "1.85" From d5e6a15fb5ff4cffa71b27e46e9f8dc25be69d3f Mon Sep 17 00:00:00 2001 From: Jonathan Pallant Date: Tue, 21 Jul 2026 14:10:29 +0100 Subject: [PATCH 2/8] Bump cortex-m to 0.7.8 --- cortex-m/CHANGELOG.md | 5 ++++- cortex-m/Cargo.toml | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/cortex-m/CHANGELOG.md b/cortex-m/CHANGELOG.md index b67d5345..d88407fa 100644 --- a/cortex-m/CHANGELOG.md +++ b/cortex-m/CHANGELOG.md @@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +## [v0.7.8] - 2026-07-21 + ### Deprecated - The `inline-asm` feature is now a currently a no-op, will be removed in a future major version @@ -778,7 +780,8 @@ fn main() { - Functions to get the vector table - Wrappers over miscellaneous instructions like `bkpt` -[Unreleased]: https://github.com/rust-embedded/cortex-m/compare/v0.7.7...HEAD +[Unreleased]: https://github.com/rust-embedded/cortex-m/compare/v0.7.8...HEAD +[v0.7.8]: https://github.com/rust-embedded/cortex-m/compare/v0.7.7...v0.7.8 [v0.7.7]: https://github.com/rust-embedded/cortex-m/compare/v0.7.6...v0.7.7 [v0.7.6]: https://github.com/rust-embedded/cortex-m/compare/v0.7.5...v0.7.6 [v0.7.5]: https://github.com/rust-embedded/cortex-m/compare/v0.7.4...v0.7.5 diff --git a/cortex-m/Cargo.toml b/cortex-m/Cargo.toml index 358ba721..146101da 100644 --- a/cortex-m/Cargo.toml +++ b/cortex-m/Cargo.toml @@ -8,7 +8,7 @@ name = "cortex-m" readme = "README.md" repository = "https://github.com/rust-embedded/cortex-m" edition = "2024" -version = "0.7.7" +version = "0.7.8" links = "cortex-m" # prevent multiple versions of this crate to be linked together rust-version = "1.85" From cf94fbe1ee8cbeb7863355088de9110f0bc7622a Mon Sep 17 00:00:00 2001 From: Jonathan Pallant Date: Tue, 21 Jul 2026 14:13:22 +0100 Subject: [PATCH 3/8] Fix cortex-m doc build errors. --- cortex-m/src/cmse.rs | 2 +- cortex-m/src/peripheral/sau.rs | 32 ++++++++++++++++++++------------ cortex-m/src/register/primask.rs | 5 +++-- 3 files changed, 24 insertions(+), 15 deletions(-) diff --git a/cortex-m/src/cmse.rs b/cortex-m/src/cmse.rs index 36d74475..b146fb8b 100644 --- a/cortex-m/src/cmse.rs +++ b/cortex-m/src/cmse.rs @@ -4,7 +4,7 @@ //! Extensions. //! Most of this implementation is directly inspired by the "Armv8-M Security Extensions: //! Requirements on Development Tools" document available here: -//! https://developer.arm.com/docs/ecm0359818/latest +//! //! //! Please note that the TT instructions support as described part 4 of the document linked above is //! not part of CMSE but is still present in this module. The TT instructions return the diff --git a/cortex-m/src/peripheral/sau.rs b/cortex-m/src/peripheral/sau.rs index dc00e137..6800a1f3 100644 --- a/cortex-m/src/peripheral/sau.rs +++ b/cortex-m/src/peripheral/sau.rs @@ -161,11 +161,13 @@ impl SAU { /// Disable the SAU and mark all memory Non-Secure (ALLNS mode). /// - /// Sets `CTRL.ALLNS = 1`, `CTRL.ENABLE = 0`. When the SAU is disabled with ALLNS set, the - /// entire address space is treated as Non-Secure (subject to any IDAU overrides). Use this - /// when running entirely in Non-Secure mode with no security boundary enforcement. + /// Sets `CTRL.ALLNS = 1`, `CTRL.ENABLE = 0`. When the SAU is disabled with + /// ALLNS set, the entire address space is treated as Non-Secure (subject to + /// any IDAU overrides). Use this when running entirely in Non-Secure mode + /// with no security boundary enforcement. /// - /// To re-enable security boundaries, call [`init`] or [`enable`] after programming regions. + /// To re-enable security boundaries, call [`init`](Self::init) or + /// [`enable`](Self::enable) after programming regions. #[inline] pub fn disable_allns(&mut self) { unsafe { @@ -175,21 +177,27 @@ impl SAU { /// Program SAU regions and enable the SAU. /// - /// This is a convenience wrapper around [`set_region`] + [`enable`]: + /// This is a convenience wrapper around [`set_region`](Self::set_region) + + /// [`enable`](Self::enable): + /// /// 1. Disables the SAU temporarily. /// 2. Programs all regions from `regions`. /// 3. Re-enables the SAU. /// - /// Memory not covered by any enabled region is treated as Secure once the SAU is enabled. + /// Memory not covered by any enabled region is treated as Secure once the + /// SAU is enabled. /// - /// To also enable the `SecureFault` exception so TrustZone violations surface as a dedicated - /// fault rather than escalating to `HardFault`, call - /// `scb.enable(cortex_m::peripheral::scb::Exception::SecureFault)` after this. + /// To also enable the `SecureFault` exception so TrustZone violations + /// surface as a dedicated fault rather than escalating to `HardFault`, call + /// `scb.enable(cortex_m::peripheral::scb::Exception::SecureFault)` after + /// this. /// /// # Errors - /// Returns [`SauError::TooManyRegions`] if `regions.len()` exceeds the number of regions - /// implemented in hardware (see [`region_numbers`]). Returns other [`SauError`] variants if - /// any region descriptor has a misaligned base or limit address. + /// Returns [`SauError::TooManyRegions`] if `regions.len()` exceeds the + /// number of regions implemented in hardware (see + /// [`region_numbers`](Self::region_numbers). Returns other [`SauError`] + /// variants if any region descriptor has a misaligned base or limit + /// address. /// /// On error the SAU is left disabled (in the state set at step 1 above). #[inline] diff --git a/cortex-m/src/register/primask.rs b/cortex-m/src/register/primask.rs index e368f728..163fee95 100644 --- a/cortex-m/src/register/primask.rs +++ b/cortex-m/src/register/primask.rs @@ -40,7 +40,7 @@ pub fn read() -> Primask { } /// Reads the entire PRIMASK register -/// Note that bits [31:1] are reserved and UNK (Unknown) +/// Note that bits `[31:1]` are reserved and UNK (Unknown) #[inline] #[asm_cfg(cortex_m)] pub fn read_raw() -> u32 { @@ -50,7 +50,8 @@ pub fn read_raw() -> u32 { } /// Writes the entire PRIMASK register -/// Note that bits [31:1] are reserved and SBZP (Should-Be-Zero-or-Preserved) +/// +/// Note that bits `[31:1]` are reserved and SBZP (Should-Be-Zero-or-Preserved) /// /// # Safety /// From 8cadff9861e09b960eaa8bcbbb7c0ebc89d87f8e Mon Sep 17 00:00:00 2001 From: Jonathan Pallant Date: Tue, 21 Jul 2026 14:13:32 +0100 Subject: [PATCH 4/8] Add missing docs for secure-mode feature --- cortex-m/src/lib.rs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/cortex-m/src/lib.rs b/cortex-m/src/lib.rs index 481505b9..b6968f34 100644 --- a/cortex-m/src/lib.rs +++ b/cortex-m/src/lib.rs @@ -49,6 +49,12 @@ //! [Linker-Plugin LTO]: https://doc.rust-lang.org/stable/rustc/linker-plugin-lto.html //! [rust-lang/rust#75940]: https://github.com/rust-lang/rust/issues/75940 //! +//! ## `secure-mode` +//! +//! Adds extra non-secure peripherals to the `Peripherals` struct. Only set when your +//! processor is running in Secure mode, and you need to control operations in nonsecure +//! mode (e.g. to bootload some nonsecure firmware). +//! //! ## `inline-asm` //! //! This feature is deprecated. From a0e00d4820d2d3f601763dcb40d8b7d68d1c259f Mon Sep 17 00:00:00 2001 From: Jonathan Pallant Date: Tue, 21 Jul 2026 14:18:18 +0100 Subject: [PATCH 5/8] Also bump cortex-m-macros We'll keep it in sync like cortex-m-rt and cortex-m-rt-macros --- cortex-m/Cargo.toml | 2 +- cortex-m/macros/Cargo.toml | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/cortex-m/Cargo.toml b/cortex-m/Cargo.toml index 146101da..3540cab8 100644 --- a/cortex-m/Cargo.toml +++ b/cortex-m/Cargo.toml @@ -19,7 +19,7 @@ volatile-register = "0.2.2" bitfield = "0.13.2" eh0 = { package = "embedded-hal", version = "0.2.4" } eh1 = { package = "embedded-hal", version = "1.0.0" } -cortex-m-macros = { path = "macros", version = "=0.1.0" } +cortex-m-macros = { path = "macros", version = "=0.7.8" } [dependencies.serde] version = "1" diff --git a/cortex-m/macros/Cargo.toml b/cortex-m/macros/Cargo.toml index fb376de6..143ac8d6 100644 --- a/cortex-m/macros/Cargo.toml +++ b/cortex-m/macros/Cargo.toml @@ -1,6 +1,11 @@ [package] +categories = ["embedded", "no-std"] +description = "Attributes used by `cortex-m`" +documentation = "https://docs.rs/cortex-m-rt" +license = "MIT OR Apache-2.0" name = "cortex-m-macros" -version = "0.1.0" +repository = "https://github.com/rust-embedded/cortex-m" +version = "0.7.8" edition = "2024" rust-version = "1.85" From 55744dd3411cfb30125f46784e1779e757d1caae Mon Sep 17 00:00:00 2001 From: Jonathan Pallant Date: Tue, 21 Jul 2026 14:33:00 +0100 Subject: [PATCH 6/8] Fix two MSRV mentions that were wrong --- cortex-m-rt/src/lib.rs | 2 +- cortex-m/src/lib.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cortex-m-rt/src/lib.rs b/cortex-m-rt/src/lib.rs index b04fd57e..631faedc 100644 --- a/cortex-m-rt/src/lib.rs +++ b/cortex-m-rt/src/lib.rs @@ -500,7 +500,7 @@ //! //! # Minimum Supported Rust Version (MSRV) //! -//! The MSRV of this release is Rust 1.61.0. +//! The MSRV of this release is Rust 1.85. // # Developer notes // diff --git a/cortex-m/src/lib.rs b/cortex-m/src/lib.rs index b6968f34..a3ed32e4 100644 --- a/cortex-m/src/lib.rs +++ b/cortex-m/src/lib.rs @@ -63,7 +63,7 @@ //! //! # Minimum Supported Rust Version (MSRV) //! -//! This crate is guaranteed to compile on stable Rust 1.61 and up. It *might* +//! This crate is guaranteed to compile on stable Rust 1.85 and up. It *might* //! compile with older versions but that may change in any new patch release. #![deny(missing_docs)] From 11138603556d8742b5b5094b8294f022b4e94f82 Mon Sep 17 00:00:00 2001 From: Jonathan Pallant Date: Tue, 21 Jul 2026 14:43:22 +0100 Subject: [PATCH 7/8] Fix doc rendering for MCR/MRC functions. --- cortex-m/src/asm.rs | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/cortex-m/src/asm.rs b/cortex-m/src/asm.rs index f4090832..ac211925 100644 --- a/cortex-m/src/asm.rs +++ b/cortex-m/src/asm.rs @@ -465,10 +465,13 @@ core::arch::global_asm!( ); /// This instruction moves one Register to a Coprocessor Register. +/// /// This function generates inline assembly and needs the instruction configuration /// during compilation time (i.e. as `const`). +/// /// The values of the constants required by this function should be defined by /// the coprocessor's reference manual. +/// /// - CP: The coprocessor's index. /// - OP1: First optional operation for the coprocessor. /// - CRN: Coprocessor register N. @@ -494,10 +497,13 @@ pub unsafe fn mcr(a: u32, b: u32 } /// This instruction moves two Coprocessor Registers to Registers. +/// /// This function generates inline assembly and needs the instruction configuration /// during compilation time (i.e. as `const`). +/// /// The values of the constants required by this function should be defined by /// the coprocessor's reference manual. +/// /// - CP: The coprocessor's index. /// - OP1: First optional operation for the coprocessor. /// - CRM: Coprocessor register M. From 8c5761a1cb9aa158d003e45710c535e106662b96 Mon Sep 17 00:00:00 2001 From: Jonathan Pallant Date: Tue, 21 Jul 2026 14:43:44 +0100 Subject: [PATCH 8/8] Another doc typo Found old mention of ptr method, when you should use the PTR constant. --- cortex-m/src/peripheral/mod.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cortex-m/src/peripheral/mod.rs b/cortex-m/src/peripheral/mod.rs index d69ea0aa..39cbe1c9 100644 --- a/cortex-m/src/peripheral/mod.rs +++ b/cortex-m/src/peripheral/mod.rs @@ -37,7 +37,7 @@ //! let cyccnt = DWT::cycle_count(); //! ``` //! -//! The singleton property can be *unsafely* bypassed using the `ptr` static method which is +//! The singleton property can be *unsafely* bypassed using the `PTR` associated const which is //! available on all the peripheral types. This method is a useful building block for implementing //! safe higher level abstractions. //!