Part of the RISC-V port. Counterpart of the arm64 SMMU item #18.
The RISC-V IOMMU (drivers/iommu/riscv/) has one device-context table per IOMMU, host-owned. The spawn DTB omits the IOMMU node and strips iommus, so the spawn uses direct DMA. The host must make that safe:
- On device assignment install either a bypass device context (parity with x86 today) or a second-stage table covering exactly the instance's memory grant so a buggy spawn driver cannot DMA into the host.
- Update the second-stage mapping on memory hot-add/remove and tear it down when the device returns.
- Non-coherent masters:
dma-noncoherent in the instance DTB and Zicbom in the spawn (CONFIG_RISCV_ISA_ZICBOM); QEMU virt PCIe is coherent.
Can be deferred for first bring-up on QEMU; required before any multi-tenant use on hardware.
Part of the RISC-V port. Counterpart of the arm64 SMMU item #18.
The RISC-V IOMMU (
drivers/iommu/riscv/) has one device-context table per IOMMU, host-owned. The spawn DTB omits the IOMMU node and stripsiommus, so the spawn uses direct DMA. The host must make that safe:dma-noncoherentin the instance DTB and Zicbom in the spawn (CONFIG_RISCV_ISA_ZICBOM); QEMU virt PCIe is coherent.Can be deferred for first bring-up on QEMU; required before any multi-tenant use on hardware.