riscv: APLIC tenant mode and per-hart IMSIC MSI for spawn kernels

[congwang-mk]

Part of the RISC-V port. Needed for AIA platforms (QEMU virt with aia=aplic-imsic, future server SoCs).

IMSIC: one interrupt file per hart at a known physical address; an MSI is a 32-bit write of the identity to that file. irq-riscv-imsic-state.c is already per-CPU, so a spawn allocates identities in its own harts' files and composes MSI messages itself (imsic_irq_compose_vector_msg()). No shared command queue; the arm64 host-proxied ITS (#16) has no RISC-V counterpart.

• IMSIC: verify the stock driver only touches the files of harts in this kernel (it does today via per-CPU state) and exclude IMSIC_MK_ID from the allocator. Guest files are per-hart too, so a spawn started in HS-mode can run KVM with AIA.
• APLIC in MSI mode (irq-riscv-aplic-msi.c / -main.c): domaincfg and msicfg (aplic_init_hw_global()) are global and host-owned; sourcecfg[i]/target[i] are per source. Tenant mode: skip aplic_init_hw_global(), refuse sources outside the granted ranges, write target[] only for granted sources and only pointing at this kernel's harts (hart index + guest index 0 + EIID).
• APLIC direct mode (no IMSIC): behaves like PLIC; reuse the PLIC tenant approach.
• PCIe MSI/MSI-X for assigned devices then works with the stock pci-msi path over the spawn's IMSIC domain; nothing to proxy.
• Host side: manifest carries APLIC source ranges; host masks handed-out sources and retakes on teardown.

Test: virtio-pci device assigned to a spawn on QEMU aia=aplic-imsic, MSI-X interrupts land on spawn harts, host devices unaffected.