Add a Specific Implementation for RISC-V ISA AI Extensions

[antoinecarme]

ML2CPP can generate specific C++ code with RISC-V extensions allowing all scikit-learn, pytorch, caret ML models to be deployable natively on this platform.

RISC-V extensions have the advantage to be non-proprietary.

This is a place holder for following the recent efforts on designing RISC-V specific extensions for AI/ML.

No public hardware is available yet.

Sifive Intelligence X280 CPU is an interesting start point. https://www.sifive.com/blog/introduction-to-the-sifive-intelligence-x280

[antoinecarme]

[antoinecarme]

https://www.sifive.com/document-file/x280-datasheet

[antoinecarme]

https://cambrian-ai.com/sifive-is-leading-the-way-for-innovation-on-risc-v/

[antoinecarme]

First SBCs with Sifive CPU hit the market (No AI Extensions ;)

https://www.kickstarter.com/projects/starfive/visionfive-2

[antoinecarme]

https://github.com/riscv/riscv-v-spec

https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc

[antoinecarme]

[antoinecarme]

Fastest way to do horizontal SSE vector sum (or other reduction)

[antoinecarme]

SiFive Tech Talk on Accelerating AI: Past, Present, and Future
by Krste Asanovic

https://www.youtube.com/watch?v=8n2HLp2gtYs

“V” Vector Extension Proposal
Krste Asanovic, UC Berkeley & SiFive

https://www.youtube.com/watch?v=K2CGz1pzNXo

[antoinecarme]

https://www.sifive.com/blog/10-important-things-to-know-about-sifive-vectors

[antoinecarme]

RISC-V Workshop Barcelona May 7th 2018

Vector ISA

Presentation by Roger Espasa at Esperanto Technologies on May 7, 2018 at the RISC-V Workshop in Barcelona, hosted by Barcelona Supercomputing Center and Universitat Politecnica de Catalunya in Barcelona, Spain.

https://www.youtube.com/watch?v=S4fxBZD79gc

[antoinecarme]

Try using c++ Standard Data-parallel vector library when available (Allow all SIMD implementations : MMX, SSE, AVX-512, ARM Neon, IBM, ...)

https://en.cppreference.com/w/cpp/experimental/simd
https://github.com/VcDevel/std-simd
https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=libstdc%2B%2B-v3/include/experimental/simd;hb=HEAD

[antoinecarme]

antoine@z600:~$ vdir /usr/include/c++/11/experimental/bits/
fs_dir.h                lfts_config.h           simd_builtin.h          simd.h                  
simd_scalar.h           fs_fwd.h                net.h                   simd_converter.h        
simd_math.h             simd_x86_conversions.h  fs_ops.h                numeric_traits.h        
simd_detail.h           simd_neon.h             simd_x86.h              fs_path.h               
shared_ptr.h            simd_fixed_size.h       simd_ppc.h              string_view.tcc   

[antoinecarme]

SiFive P670 and P470 RISC-V processors feature RISC-V Vector Extensions

https://www.cnx-software.com/2022/11/02/sifive-p670-and-p470-risc-v-processors-add-risc-v-vector-extensions/

[antoinecarme]

RISC-V has standardized a series of standard extensions beyond the integer base instructions which can be implemented or omitted as desired depending on the design goals (e.g. energy/area/performance/storage goals).

https://en.wikichip.org/wiki/risc-v/standard_extensions

[antoinecarme]