From ffa498f54abc270c6ca6bd1850b0929a21135884 Mon Sep 17 00:00:00 2001 From: Lwazi Dube Date: Thu, 16 Jul 2026 01:40:44 -0400 Subject: [PATCH] boards/mips: Add networking support to CI20 board Introduce networking capabilities to the Creator CI20 board by leveraging the pre-existing dm9000 ethernet driver. To achieve this, the following changes were made: - Integrated the jz4780 GPIO module to properly configure and enable the interrupt pin required by the ethernet controller. - Added `dm90x0.h` to export the dm9000 initialization function, allowing the board-specific setup code to initialize the network interface. Signed-off-by: Lwazi Dube --- .../jz4780/boards/mips-creator-ci20/index.rst | 12 +- arch/mips/src/jz4780/Make.defs | 2 +- arch/mips/src/jz4780/jz4780_decodeirq.c | 10 + arch/mips/src/jz4780/jz4780_gpio.c | 212 ++++++++++++ arch/mips/src/jz4780/jz4780_gpio.h | 310 ++++++++++++++++++ boards/mips/jz4780/ci20/configs/net/defconfig | 83 +++++ boards/mips/jz4780/ci20/include/board.h | 2 + boards/mips/jz4780/ci20/src/Makefile | 2 +- boards/mips/jz4780/ci20/src/ci20_network.c | 60 ++++ include/nuttx/net/dm90x0.h | 59 ++++ 10 files changed, 749 insertions(+), 3 deletions(-) create mode 100644 arch/mips/src/jz4780/jz4780_gpio.c create mode 100644 arch/mips/src/jz4780/jz4780_gpio.h create mode 100644 boards/mips/jz4780/ci20/configs/net/defconfig create mode 100644 boards/mips/jz4780/ci20/src/ci20_network.c create mode 100644 include/nuttx/net/dm90x0.h diff --git a/Documentation/platforms/mips/jz4780/boards/mips-creator-ci20/index.rst b/Documentation/platforms/mips/jz4780/boards/mips-creator-ci20/index.rst index e2d7f6d74ab8b..40437a42c1f9f 100644 --- a/Documentation/platforms/mips/jz4780/boards/mips-creator-ci20/index.rst +++ b/Documentation/platforms/mips/jz4780/boards/mips-creator-ci20/index.rst @@ -15,8 +15,9 @@ Supported Features ================== * Single 1.2GHz MIPS32 processor -* UART0 on Raspberry PI connector * 256MiB DRAM +* UART0 on Raspberry PI connector +* Fast Ethernet (DM9000) Configurations ============== @@ -56,3 +57,12 @@ Basic serial console access to the NSH shell. Then use some serial console client (minicom, picocom, teraterm, etc) configured to 115200 8n1 without software or hardware flow control. + +net +--- + +* Basic serial console access to the NSH shell. +* Networking support through the RJ45 connector. + +The telnet daemon is included, so the CI20 board can be connected to through telnet. + diff --git a/arch/mips/src/jz4780/Make.defs b/arch/mips/src/jz4780/Make.defs index 884c425e5b3d7..8684ef2b249ed 100644 --- a/arch/mips/src/jz4780/Make.defs +++ b/arch/mips/src/jz4780/Make.defs @@ -46,4 +46,4 @@ endif CHIP_ASRCS = CHIP_CSRCS = jz4780_lowinit.c jz4780_exception.c jz4780_decodeirq.c -CHIP_CSRCS += jz4780_irq.c jz4780_timerisr.c +CHIP_CSRCS += jz4780_irq.c jz4780_timerisr.c jz4780_gpio.c diff --git a/arch/mips/src/jz4780/jz4780_decodeirq.c b/arch/mips/src/jz4780/jz4780_decodeirq.c index e5202859efa69..69affc3731196 100644 --- a/arch/mips/src/jz4780/jz4780_decodeirq.c +++ b/arch/mips/src/jz4780/jz4780_decodeirq.c @@ -38,6 +38,7 @@ #include #include "mips_internal.h" +#include "jz4780_gpio.h" /**************************************************************************** * Pre-processor Definitions @@ -122,6 +123,15 @@ uint32_t *jz4780_decodeirq(uint32_t *regs) irq = IRQ_TMR0 + n; } } + else if (irq == JZ4780_IRQ_GPIOE) + { +#ifdef CONFIG_ARCH_BOARD_CI20 + + /* Ack the ethernet interrupt */ + + putreg32(BOARD_ETH_FLG, JZ4780_BASE_GPIOE + GPIO_FLGC); +#endif + } if (irq >= 0) { diff --git a/arch/mips/src/jz4780/jz4780_gpio.c b/arch/mips/src/jz4780/jz4780_gpio.c new file mode 100644 index 0000000000000..895a425a95877 --- /dev/null +++ b/arch/mips/src/jz4780/jz4780_gpio.c @@ -0,0 +1,212 @@ +/**************************************************************************** + * arch/mips/src/jz4780/jz4780_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "mips_internal.h" + +#include "jz4780_gpio.h" + +#if CHIP_NPORTS > 0 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_configgpio_lock = SP_UNLOCKED; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* This table is used to map a port number to a port base address. */ + +const uintptr_t g_gpiobase[CHIP_NPORTS] = +{ + JZ4780_BASE_GPIOA +#if CHIP_NPORTS > 1 + , JZ4780_BASE_GPIOB +#endif +#if CHIP_NPORTS > 2 + , JZ4780_BASE_GPIOC +#endif +#if CHIP_NPORTS > 3 + , JZ4780_BASE_GPIOD +#endif +#if CHIP_NPORTS > 4 + , JZ4780_BASE_GPIOE +#endif +#if CHIP_NPORTS > 5 + , JZ4780_BASE_GPIOF +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: Inline PIN set field extractors + ****************************************************************************/ + +static inline unsigned int jz4780_portno(pinset_t pinset) +{ + return ((pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT); +} + +static inline unsigned int jz4780_pinno(pinset_t pinset) +{ + return ((pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: jz4780_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin + * + * Returned Value: + * OK on success; negated errno on failure. + * + ****************************************************************************/ + +int jz4780_configgpio(pinset_t p) +{ + unsigned int port = jz4780_portno(p); + unsigned int pin = jz4780_pinno(p); + uint32_t mask = (1 << pin); + uintptr_t base; + irqstate_t flags; + + /* Verify that the port number is within range */ + + if (port < CHIP_NPORTS) + { + /* Get the base address of the ports */ + + base = g_gpiobase[port]; + + flags = spin_lock_irqsave(&g_configgpio_lock); + + putreg32(mask, base + ((MODE_BIT_PXT0 & p) ? GPIO_PXT0S : GPIO_PXT0C)); + putreg32(mask, base + ((MODE_BIT_PXT1 & p) ? GPIO_PXT1S : GPIO_PXT1C)); + putreg32(mask, base + ((MODE_BIT_MSK & p) ? GPIO_MSKS : GPIO_MSKC)); + putreg32(mask, base + ((MODE_BIT_INT & p) ? GPIO_INTS : GPIO_INTC)); + + putreg32(mask, base + ((GPIO_PULL_EN & p) ? GPIO_PENS : GPIO_PENC)); + + spin_unlock_irqrestore(&g_configgpio_lock, flags); + + return OK; + } + + return -EINVAL; +} + +/**************************************************************************** + * Name: jz4780_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void jz4780_gpiowrite(pinset_t pinset, bool value) +{ + unsigned int port = jz4780_portno(pinset); + unsigned int pin = jz4780_pinno(pinset); + uintptr_t base; + + /* Verify that the port number is within range */ + + if (port < CHIP_NPORTS) + { + /* Get the base address of the ports */ + + base = g_gpiobase[port]; + + /* Set or clear the output */ + + if (value) + { + putreg32(1 << pin, base + GPIO_PXT0S); + } + else + { + putreg32(1 << pin, base + GPIO_PXT0C); + } + } +} + +/**************************************************************************** + * Name: jz4780_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool jz4780_gpioread(pinset_t pinset) +{ + unsigned int port = jz4780_portno(pinset); + unsigned int pin = jz4780_pinno(pinset); + uintptr_t base; + + /* Verify that the port number is within range */ + + if (port < CHIP_NPORTS) + { + /* Get the base address of the ports */ + + base = g_gpiobase[port]; + + /* Get and return the input value */ + + return (getreg32(base + GPIO_PXPIN) & (1 << pin)) != 0; + } + + return false; +} + +#endif /* CHIP_NPORTS > 0 */ diff --git a/arch/mips/src/jz4780/jz4780_gpio.h b/arch/mips/src/jz4780/jz4780_gpio.h new file mode 100644 index 0000000000000..7e35a411e885c --- /dev/null +++ b/arch/mips/src/jz4780/jz4780_gpio.h @@ -0,0 +1,310 @@ +/***************************************************************************** + * arch/mips/src/jz4780/jz4780_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + *****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_JZ4780_JZ4780_GPIO_H +#define __ARCH_MIPS_SRC_JZ4780_JZ4780_GPIO_H + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include +#include +#include +#include + +/***************************************************************************** + * Pre-processor Definitions + *****************************************************************************/ + +#define JZ4780_BASE_GPIOA 0xB0010000U +#define JZ4780_BASE_GPIOB 0xB0010100U +#define JZ4780_BASE_GPIOC 0xB0010200U +#define JZ4780_BASE_GPIOD 0xB0010300U +#define JZ4780_BASE_GPIOE 0xB0010400U +#define JZ4780_BASE_GPIOF 0xB0010500U + +#define GPIO_PXPIN 0x00 + +#define GPIO_INT 0x10 +#define GPIO_INTS 0x14 +#define GPIO_INTC 0x18 + +#define GPIO_MSK 0x20 +#define GPIO_MSKS 0x24 +#define GPIO_MSKC 0x28 + +#define GPIO_PXT1 0x30 +#define GPIO_PXT1S 0x34 +#define GPIO_PXT1C 0x38 + +#define GPIO_PXT0 0x40 +#define GPIO_PXT0S 0x44 +#define GPIO_PXT0C 0x48 + +#define GPIO_FLG 0x50 +#define GPIO_FLGC 0x58 + +#define GPIO_PEN 0x70 +#define GPIO_PENS 0x74 +#define GPIO_PENC 0x78 + +/* GPIO settings */ + +#define MODE_BIT_PXT0 (1 << GPIO_MODE_SHIFT) +#define MODE_BIT_PXT1 (2 << GPIO_MODE_SHIFT) +#define MODE_BIT_MSK (4 << GPIO_MODE_SHIFT) +#define MODE_BIT_INT (8 << GPIO_MODE_SHIFT) + +#define GPIO_MODE_SHIFT (9) /* Bits 9-12: I/O mode */ +#define GPIO_MODE_MASK (0xF << GPIO_MODE_SHIFT) + +# define GPIO_MODE_DEVICE0 (0x0 << GPIO_MODE_SHIFT) /* 0000 Device 0 */ +# define GPIO_MODE_DEVICE1 (0x1 << GPIO_MODE_SHIFT) /* 0001 Device 1 */ +# define GPIO_MODE_DEVICE2 (0x2 << GPIO_MODE_SHIFT) /* 0010 Device 2 */ +# define GPIO_MODE_DEVICE3 (0x3 << GPIO_MODE_SHIFT) /* 0011 Device 3 */ + +# define GPIO_MODE_OUTPUT0 (0x4 << GPIO_MODE_SHIFT) /* 0100 GPIO out 0 */ +# define GPIO_MODE_OUTPUT1 (0x5 << GPIO_MODE_SHIFT) /* 0101 GPIO out 1 */ +# define GPIO_MODE_INPUT (0x6 << GPIO_MODE_SHIFT) /* 0110 GPIO in */ +# define GPIO_MODE_INPUT_TOO (0x7 << GPIO_MODE_SHIFT) /* 0111 GPIO in */ + +# define GPIO_MODE_INTR_LOW (0x8 << GPIO_MODE_SHIFT) /* 1000 low level interrupt */ +# define GPIO_MODE_INTR_HIGH (0x9 << GPIO_MODE_SHIFT) /* 1001 high level interrupt */ +# define GPIO_MODE_INTR_FALL (0xA << GPIO_MODE_SHIFT) /* 1010 falling edge intr. */ +# define GPIO_MODE_INTR_RISE (0xB << GPIO_MODE_SHIFT) /* 1011 rising edge intr */ + +/* Interrupt masked and flag is record (*IMF) */ + +# define GPIO_MODE_IMF_LOW (0xC << GPIO_MODE_SHIFT) /* 1100 low level interrupt */ +# define GPIO_MODE_IMF_HIGH (0xD << GPIO_MODE_SHIFT) /* 1101 high level interrupt */ +# define GPIO_MODE_IMF_FALL (0xE << GPIO_MODE_SHIFT) /* 1110 falling edge intr. */ +# define GPIO_MODE_IMF_RISE (0xF << GPIO_MODE_SHIFT) /* 1111 rising edge intr */ + +#define GPIO_PULL_EN (1 << 8) /* Bit 8: pull-up/pull-down */ + +#define GPIO_PORT_SHIFT (5) /* Bits 5-7: Port number */ +#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) +# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) +# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) +# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) +# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) +# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) +# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) + +#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */ +#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT) + +# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) +# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) +# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) +# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) +# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) +# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) +# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) +# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) +# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) +# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) +# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) +# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) +# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) +# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) +# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) +# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) +# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) + +/***************************************************************************** + * Public Types + *****************************************************************************/ + +#ifndef __ASSEMBLY__ + +typedef uint32_t pinset_t; + +/***************************************************************************** + * Public Data + *****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* This table can be used to map a port number to a IOPORT base address. For + * example, an index of zero would correspond to IOPORTA, one with IOPORTB, + * etc. + */ + +EXTERN const uintptr_t g_gpiobase[CHIP_NPORTS]; + +/***************************************************************************** + * Public Function Prototypes + *****************************************************************************/ + +/***************************************************************************** + * Name: jz4780_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin (the + * interrupt will be configured when jz4780_attach() is called). + * + * Returned Value: + * OK on success; negated errno on failure. + * + *****************************************************************************/ + +int jz4780_configgpio(pinset_t cfgset); + +/***************************************************************************** + * Name: jz4780_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + *****************************************************************************/ + +void jz4780_gpiowrite(pinset_t pinset, bool value); + +/***************************************************************************** + * Name: jz4780_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + *****************************************************************************/ + +bool jz4780_gpioread(pinset_t pinset); + +/***************************************************************************** + * Name: jz4780_gpioirqinitialize + * + * Description: + * Initialize logic to support a GPIO change notification interrupts. This + * function is called internally by the system on power up and should not be + * called again. + * + *****************************************************************************/ + +#ifdef CONFIG_JZ4780_GPIOIRQ +void jz4780_gpioirqinitialize(void); +#else +# define jz4780_gpioirqinitialize() +#endif + +/***************************************************************************** + * Name: jz4780_gpioattach + * + * Description: + * Attach an interrupt service routine to a GPIO interrupt. This will also + * reconfigure the pin as an interrupting input. The change notification + * number is associated with all interrupt-capable GPIO pins. The + * association could, however, differ from part to part and must be provided + * by the caller. + * + * When an interrupt occurs, it is due to a change on the GPIO input pin. + * In that case, all attached handlers will be called. Each handler must + * maintain state and determine if the underlying GPIO input value changed. + * + * pinset - GPIO pin configuration + * handler - Interrupt handler (may be NULL to detach) + * arg - The argument that accompanies the interrupt + * + * Returned Value: + * Zero (OK) is returned on success. A negated error value is returned on + * any failure to indicate the nature of the failure. + * + *****************************************************************************/ + +#ifdef CONFIG_JZ4780_GPIOIRQ +int jz4780_gpioattach(uint32_t pinset, xcpt_t handler, void *arg); +#else +# define jz4780_gpioattach(p,h,a) (0) +#endif + +/***************************************************************************** + * Name: jz4780_gpioirqenable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + *****************************************************************************/ + +#ifdef CONFIG_JZ4780_GPIOIRQ +void jz4780_gpioirqenable(pinset_t pinset); +#else +# define jz4780_gpioirqenable(irq) +#endif + +/***************************************************************************** + * Name: jz4780_gpioirqdisable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + *****************************************************************************/ + +#ifdef CONFIG_JZ4780_GPIOIRQ +void jz4780_gpioirqdisable(pinset_t pinset); +#else +# define jz4780_gpioirqdisable(irq) +#endif + +/***************************************************************************** + * Function: jz4780_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the provided base address + * + *****************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO_INFO +void jz4780_dumpgpio(uint32_t pinset, const char *msg); +#else +# define jz4780_dumpgpio(p,m) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_JZ4780_JZ4780_GPIO_H */ diff --git a/boards/mips/jz4780/ci20/configs/net/defconfig b/boards/mips/jz4780/ci20/configs/net/defconfig new file mode 100644 index 0000000000000..0a033557465db --- /dev/null +++ b/boards/mips/jz4780/ci20/configs/net/defconfig @@ -0,0 +1,83 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NDEBUG is not set +CONFIG_16550_ADDRWIDTH=32 +CONFIG_16550_REGWIDTH=32 +CONFIG_16550_SUPRESS_CONFIG=y +CONFIG_16550_UART0=y +CONFIG_16550_UART0_BASE=0xB0030000 +CONFIG_16550_UART0_CLOCK=14745600 +CONFIG_16550_UART0_IRQ=51 +CONFIG_16550_UART0_SERIAL_CONSOLE=y +CONFIG_16550_UART=y +CONFIG_ARCH="mips" +CONFIG_ARCH_BOARD="ci20" +CONFIG_ARCH_BOARD_CI20=y +CONFIG_ARCH_CHIP="jz4780" +CONFIG_ARCH_CHIP_JZ4780=y +CONFIG_ARCH_MIPS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=72450 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ERROR=y +CONFIG_DEBUG_FS_WARN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DM9X_BASE=0xB6000000 +CONFIG_DM9X_BUSWIDTH8=y +CONFIG_DM9X_IRQ=13 +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_GRAN=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_MIPS32_DCACHE=y +CONFIG_MIPS32_DCACHE_SIZE=32768 +CONFIG_MIPS32_DLINE_SIZE=32 +CONFIG_MIPS32_ICACHE=y +CONFIG_MIPS32_ICACHE_SIZE=32768 +CONFIG_MIPS32_ILINE_SIZE=32 +CONFIG_MIPS32_KSEG0_IBASE=0x80000000 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NET=y +CONFIG_NETDEV_IFINDEX=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETINIT_DRIPADDR=0xc0a80250 +CONFIG_NETINIT_IPADDR=0xc0a80203 +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_DM90x0=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=33554432 +CONFIG_RAM_START=0x80000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=50 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=7 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2026 +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_UBOOT_UIMAGE=y +CONFIG_UIMAGE_ENTRY_POINT=0x800004AC +CONFIG_UIMAGE_LOAD_ADDRESS=0x80000180 +CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/mips/jz4780/ci20/include/board.h b/boards/mips/jz4780/ci20/include/board.h index b01d367356f41..c17307a01e53e 100644 --- a/boards/mips/jz4780/ci20/include/board.h +++ b/boards/mips/jz4780/ci20/include/board.h @@ -37,6 +37,8 @@ * Pre-processor Definitions ****************************************************************************/ +#define BOARD_ETH_FLG (1 << 19) + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/boards/mips/jz4780/ci20/src/Makefile b/boards/mips/jz4780/ci20/src/Makefile index 75e98ad71421e..0201344af99e5 100644 --- a/boards/mips/jz4780/ci20/src/Makefile +++ b/boards/mips/jz4780/ci20/src/Makefile @@ -23,6 +23,6 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = jz4780_boot.c jz4780_bringup.c +CSRCS = jz4780_boot.c jz4780_bringup.c ci20_network.c include $(TOPDIR)/boards/Board.mk diff --git a/boards/mips/jz4780/ci20/src/ci20_network.c b/boards/mips/jz4780/ci20/src/ci20_network.c new file mode 100644 index 0000000000000..a4be5d8dd8adf --- /dev/null +++ b/boards/mips/jz4780/ci20/src/ci20_network.c @@ -0,0 +1,60 @@ +/**************************************************************************** + * boards/mips/jz4780/ci20/src/ci20_network.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#if defined(CONFIG_NET) && defined(CONFIG_NET_DM90x0) + +#include +#include + +#include + +#include "chip.h" +#include "mips_internal.h" + +#include "jz4780_gpio.h" +#include "ci20.h" + +/* PE19 is the ethernet interrupt input pin (ETHNET_INT in schematic) */ + +#define ETHNET_INT (GPIO_MODE_INTR_RISE | GPIO_PORTE | GPIO_PIN19) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_netinitialize + ****************************************************************************/ + +void mips_netinitialize(void) +{ + jz4780_configgpio(ETHNET_INT); + + (void)dm9x_initialize(); +} + +#endif /* CONFIG_NET && CONFIG_NET_DM90x0 */ diff --git a/include/nuttx/net/dm90x0.h b/include/nuttx/net/dm90x0.h new file mode 100644 index 0000000000000..919522d2d2f08 --- /dev/null +++ b/include/nuttx/net/dm90x0.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * include/nuttx/net/dm90x0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_NET_DM90X0_H +#define __INCLUDE_NUTTX_NET_DM90X0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: dm9x_initialize + * + * Description: + * Register a dm9x driver + * + ****************************************************************************/ + +int dm9x_initialize(void); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_NET_DM90X0_H */